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LMK03806: LVCMOS (Norm/Low) output error

JH Shin
Mastermind 7060 points
Part Number: LMK03806

Hello,

My customer is using the LMK03806 with the following setting.

LMK03806.TCS

The capture image of the LVCMOS (Norm/Low) output is as follows(Yellow=P port/ Blue=N port).

They thought the N port output would be Low, but there is clock output.

Please help us with the cause of this problem and how to fix it.

Thank you.

JH

  • 0
    TI__Mastermind 28530 points

    Hi JH,

    I can double-check this tomorrow, however I will be checking the different LVCMOS (setting P, setting N) to see if there is some mislabeling.
      - Have other LVCMOS settings been tried?

    If this is not a simple error in LVCMOS setting...

    Can you describe in more detail the test setup?  I notice that the waveforms are other aligned nor 180 degrees out of phase as I'd expect.  Are different length cables being used?

    Can you confirm if the measurement is occurring on the EVM or other customer board?
      - If customer board, do you have a schematic/PCB of the output?
      - I note that the N amplitude is less.  I'm wondering if there is some coupling or 100 ohm differential termination that is causing the measured N output to show the waveform?

    73,
    Timothy

  • 0 in reply to Timothy T
    Mastermind 7060 points

    Hi Timothy,

    Thanks for your help,

    This issue has been confirmed with a customer designed board, and the schematic can be found in the thread below.

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1024759/lmk03806-lmk03806-schematic-review/3788460#3788460

    They also checked the LVCMOS output with different seetings.

    1. LVCMOS (Norm/Inv)

    2. LVCMOS(Low/Low)

    3. LVCMOS(Norm/Norm)

    This issue occurs with only one output setup: LVCMOS(Low/Norm), LVCMOS(Low/Inv), LVCMOS(Norm/Low), LVCMOS(Inv/Low).

    This is in case of LVCMOS(Low/Inv) setting.

    Regards,

    JH

  • 0 in reply to JH Shin
    TI__Mastermind 28530 points

    Hi JH,

    I confirmed there is no issue with the logic for Norm/Off.  The schematic review shows OUT6 as LVDS.  My expectation is that the trace is routed as a differential trace (since it appears to been laid out for LVDS) and there is substantial crosstalk to from the CLKout6_P (Normal) to CLKout6_N (Off).

    If you were to decrease your frequency from 61.44 MHz to 6.144 MHz (or lower), I think you would see the off output behave as you expect.

    73,
    Timothy