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LMK00804B-Q1: 25MHz clock generation for FPGA and ETHERNET PHY

Part Number: LMK00804B-Q1
Other Parts Discussed in Thread: LMK00804B

Hello,

Below is the requirement for our design.

We have a 25MHz crystal oscillator (+/-2ppm) in our design which operates on 3.3V with 0.2V/ns slew rate. We need to generate two clock signals (25MHz) at 1.8V for FPGA and Ethernet PHY.

We are plannig to use LMK00804B for converting 3.3V clock signal to 1.8V clock and feed both FPGA and ETHERNET PHY. Our concern is on the output jitter from the device, as there is no information on the datasheet at 25MHz for the output additive jitter. Can you suggest if this part can be used for the above mentioned application.

Regards

Sudheer

  • Hi Sudheer,

    The LMK00804B does support 3.3V clock input to 1.8V output; however, using that crystal with 0.2V/ns input slew rate is not recommended. Per datasheet (see Section 7.11, Section 10.6.3, and Figure 1 below), the input slew rate should be at least 3V/ns to get optimal noise performance.

    I can provide jitter data at 25MHz next week.

    Regards,

    Jennifer

  • Hi Jennifer, 

    Thanks for the information.

    Can you suggest any other clock buffer from TI which can work with lower slew rate signals and level translates from 3.3V to 1.8V for 25MHz clock signals.

    Also can you please share any simulation/Experimental results for the output signal of LMK00804B at 25MHz and 0.2V/nS input slew rate?

    Regards

    Sudheer

  • Hi Sudheer,

    We do not have alternative buffers that support such slew rate and level translation. Please find typical jitter measurements of the LMK00804B at 25MHz and ~0.2V/ns in a room temperature setting: 553 fs.

    Input source from SMA100B signal generator:

    LMK00804B output:

    Regards,

    Jennifer