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clock ads5282 using CDCE62005

Other Parts Discussed in Thread: ADS5282EVM, CDCE62005, CDCE62005EVM, CDCE72010

Hello to all,

I would like to clock the ADS5282EVM board using the CDCE62005 clock generator provided by TI.

At the moment i succesfully digitize a sine wave, using a HP clock generator which provides to the ADS5282EVM board a 10MHz clock input.

I would like to clock the ADC using higher frequencies in order to achieve the full sampling rate (60Msps) of the ADC. Thus i chose to use the CDCE62005EVM.

i am using the crystal oscillator provided in the board as a refernece frequency. The ADC works pretty well for a 10MHz frequency provided by the CDCE using a LVCMOS output signal without termination.

the problem is that it not works for higher frequencies...

i would like to ask if i should provide some other reference frequency in the CDCE?

Or the problem may rely on the vhdl code that deserialize data from the ADC to my FPGA board?

In what way should i use the CDCE to provide clocks (20MHz,30MHz,40Mhz,50MHz,60MHz) to the ADC without using external reference from function generators.

I bought this board as a cheap solution for clocking the ADC at higher frequencies than 10MHz because my HP generator provides a maximum frequency of only 10 MHz.



  • Hi,

    I'd like to move this thread to the Clocks forum since you are asking about how to get the clocks you want from the CDCE62005 EVM, and the reference for that clocking device.



    Richard P.

  • 7206.CDCE62005gen20MHz30MHzand60MHz.iniSorry for the late reply, please find attached the recommended setup to generate out of the EVM 20MHz, 30MHz, 40MHz and another one that generates 50MHz, and a separate one for 40MHz. That way the maximum PD frequency could be achieved, that would result in a better rms jitter at the output.


    In order to find out if the CDCE62005 would be suitable for the bits of precision we would like to achieve with the chosen ADC the following steps should be followed in order to find out the sampling clock jitter budget:


    -Target bits of precision and SNR (SNR = 6.02B . n + 1.76dB), where n is the target number of bits. In this example the jitter budjet of the sampling clock would be calculated for the maximum bits of precision specified in the selected ADC datasheet, for 12 bits, the SNR is 74dB.


    By using the formula of SNR=-20log(2*pi*fmax*Jitter) the maximum jitter at the sampling clock to achieve that precision can be calculated back. Taking into account that jitter=sqrt(apertureJitter^2 +samplingClockJitter^2), we can calculate what is the maximum rms that we could handle in the sampling clock in order to achieve 12 bits of precision for the ADC, by substituting in the formula apertureJitter from page 12 of the ADC datasheet.


    The samplingClockJitter should be 346fs rms in order to get 12 bits of precision with the ADC selected. That is achievable by the CDCE62005 but special care must be taken on the loop bandwidth and the phase detector frequency in order to be able to achieve that performance with the CDCE62005. Usually for ADCs the CDCE72010 is recommended, although it requires external VCXO and loop bandwidth better performances and therefore more bits of precision can be achieved as the bits of precision and the jitter of the sampling clock are related to each other. In your case the CDCE62005 would be a good option as the target is a maximum of 12 bits of precision.