Hi
We plan to use the clock distributor LMK04828 in our project. While we want the chip to be powerdown for all the CLKout ports, when we power up the IC.
From the description for the registers about the CLKoutX_Y below, some of the CLKout are enable when power on. It seems we could get undesired clock at the CLKout port which will inject into the FPAG and to disturb our program.
Could you please help us to check if we can modify this default setting? That means we plan to use no output clock at all the CLKoutX_Y ports when we power up this chip.
With many thanks.