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LMK04828: LMK04828 default setting for CLKoutX_Y

Part Number: LMK04828

Hi 

We plan to use the clock distributor LMK04828 in our project. While we want the chip to be powerdown for all the CLKout ports, when we power up the IC.

From the description for the registers about the CLKoutX_Y below, some of the CLKout are enable when power on. It seems we could get undesired clock at the CLKout port which will inject into the FPAG and to disturb our program.

Could you please help us to check if we can modify this default setting? That means we plan to use no output clock at all the CLKoutX_Y ports when we power up this chip.

With many thanks.

  • Hi,

    I am afraid, but these settings are silicon default and can be change after programming the device. Just after powering up the device, run CLKoutX_Y_PD setting after reset and will not get any undesired clocks out.

    or may be provide the clocks to FPGA from the default power down channels (CLKout0_1, CLKout2_3, etc), which will not give any undesired clocks.

    Thanks!

    Regards,
    Ajeet Pal