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LMK1D1204: output level if not terminated

Hans
Genius 12705 points
Part Number: LMK1D1204
Other Parts Discussed in Thread: LMK1D1208

Hello Team,

may I ask you to provide the voltage levels in case the outputs are not terminated with 100 Ohm for the supply voltage of

Vdd     VOUTP or VOUTN high level

3.3V       ?

2.5V       ?

1.8V       ?

Thanks and Best Regards,

Hans

  • 0
    TI__Expert 6110 points

    Hi Hans, 

    I can run an IBIS model simulation to check this, although the 2.5V/3.3V modes are combined into one model. Do you have another device or load you'd like me to test at the output? If I run the simulation with no load VOUT is essentially rail-to-rail as shown in the picture below (Vdd = 1.8V). 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    TI__Genius 12705 points

    Hi Connor,

    so for Vdd = 2.5V and 3.3V the outputs will rise to the rails? It is really important because the buffer will be connected to an FPGA and the termination will be set after FPGA initialization. So in order not to violate the FPGA input level specs during power up we need a solid answer on this questions. Ideally tested on HW!

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Expert 6110 points

    Hi Hans, 

    The simulation shows similar results with the 2.5/3.3V model, with the peak-to-peak voltage at 3.75V. Do you have any information about the internal resistance of the FPGA, or anything else I can add to the load in the simulation? I believe this will provide much more accurate results. I agree, it would be best to test this on hardware. We don't have any LMK1D1208 EVMs in our office, but I placed an order to have some shipped and I can keep you updated with any test results. 

    Regards, 

    Connor

  • 0 in reply to Connor Lewis
    TI__Genius 12705 points

    Hi Connor,

    can you confirm that Vout will be limited to 3.75Vpp for Vdd=1.8V, 2.5V and 3.3V, please? If not, we really need to wait for the measurements.

    Thanks and Best Regards, Hans

  • 0 in reply to Hans
    TI__Expert 6110 points

    Hi Hans, 

    I checked with the design team and confirmed this is correct. LVDS format has a current-mode driver, so if there isn't a load resistor then the output rails out. Each output would swing from ~0.1V to ~1.8V (raw VDD when VDD = 1.8, regulated 1.8V for 2.5/3.3V). Let me know if you still need me to test in hardware. 

    Regards, 

    Connor

  • 0 in reply to Connor Lewis
    TI__Genius 12705 points

    Hi Connor,

    thanks for confirmation. Would it be possible to add the parameter "Vout High, not terminated" into the data sheet, please? Ideally as a max value or at least as a typical value?

    Thanks and Best Regards, Hans