I am currently using CDCE(L)925 for generating a system clock. The input is 96MHz with a target output of 192MHz on Y1. As of right now I can get the output to match the input clock or have Pdiv1 divide it. However, I am not able to get the multiplier to work in the PLL1 Configuration Register. I have attatched my code, where the offset is represented as a number in each config. I believe that the registers I have written to should increase the frequency but I am not observing any changes regardless how I configure the PLL1 register.
Thank you,
Kyle
# input clock selection & set slave address to 0
self.pll.NO_BLOCK.GENERIC_CONFIG1.CONFIG1.value = 0b00001000
self.pll.NO_BLOCK.GENERIC_CONFIG2.CONFIG2.value = 0b00111100
self.pll.NO_BLOCK.GENERIC_CONFIG3.CONFIG3.value = 0b00000010
# Y1 output state selection
self.pll.NO_BLOCK.GENERIC_CONFIG4.CONFIG4.value = 0b01000010
# FS1_x frequency selection
self.pll.NO_BLOCK.PLL1_CONFIG3.CONFIG3.value = 0b00000000
# PLL Mux settings
self.pll.NO_BLOCK.PLL1_CONFIG4.CONFIG4.value = 0b11101101
# Y2Y3_x output state selection
self.pll.NO_BLOCK.PLL1_CONFIG5.CONFIG5.value = 0b00000010
#
# PLL1_0 multiplier/divider for frequency
self.pll.NO_BLOCK.PLL1_CONFIG8.CONFIG8.value = 0b00000000
self.pll.NO_BLOCK.PLL1_CONFIG9.CONFIG9.value = 0b01000000
self.pll.NO_BLOCK.PLL1_CONFIG10.CONFIG10.value = 0b00000100
self.pll.NO_BLOCK.PLL1_CONFIG11.CONFIG11.value = 0b00001011
# PLL1_1 multiplier/divider for frequency
self.pll.NO_BLOCK.PLL1_CONFIG12.CONFIG12.value = 0b00000000
self.pll.NO_BLOCK.PLL1_CONFIG13.CONFIG13.value = 0b01000000
self.pll.NO_BLOCK.PLL1_CONFIG14.CONFIG14.value = 0b00000100
self.pll.NO_BLOCK.PLL1_CONFIG15.CONFIG15.value = 0b00001011
