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Original question:

LMK04828: Which clock scheme would be better to realize the lower phase noise DEVCLK generation and multichannel clock solution...

LMX2594: Will my setup of LMX2594 follow which kind of SYNC Category?

shen jie
Prodigy 185 points
Part Number: LMX2594

Hi，

I have a question about SYNC category for LMX2594. In my design, I used 1xLMK04828B + 4x LMX2594. Multi-chip synchronization is needed to sync these 4pcs LMX2594.

In my setup of LMX2594 as below figure1 shown, RFoutA will output 10GHz as device clock and RFoutB will output 4.8828125MHz  as sysref clock for high-speed ADC. So output MUX for RFoutA is switched to VCO, and output MUX for RFoutB is switched to SysRef.

My question is that

1. no channel divider will be included into the path of RFoutA, so I only choose the path as marked red in figure2 ? 

2. Category1 will be the last result, and it mentioned "SYNC Mode Not required at all". That mean SYNC mode couldn't be used?

figure1 . setup of LMX2594

figure2 . SYNC category

Best regards!!!

Jason

  • 0
    TI__Guru* 81580 points

    Hi Jason,

    1. Correct.

    2. SYNC mode not required means it is not necessary to make VCO_PHASE_SYNC=1 (no harm even if you make this bit = 1).

  • 0 in reply to Noel Fung
    Prodigy 185 points

    Hi，

    Thank for your response in time!

    Because I want to use SYSREF mode in RFoutB, VCO_PHASE_SYNC must be 1 besides SYSREF_EN =1

    If SYNC mode not required as required in Category1,  how could I implement multi-chip synchronization of these 4pcs LMX2594?

    I need to align the the edge of device clock and sysref clock for all LMX2594.

    Another question: In my setup of LMX2594 RFoutB will output sysref, so the IncludeDivide will be set to 4 automatically as below figure.1 shown. 

    Does "CHDIV" in the SYNC Category include "IncludeDivide"  as below figure.2 shown?

    If Yes, "CHDIV" in the SYNC Category is 4 too.

    figure.1 

    figure.2

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Guru* 81580 points

    Hi Jason,

    Phase alignment refers to the phase uncertainty between RF output and reference clock. The uncertainty is introduced by the dividers in the reference path and the output path. In Cat.1 sync, there is no uncertainty introduced by the dividers. As a result, RF output will always aligned with the reference clock, there is no need to enable sync mode.

    IncludedDiv is in front of the N-divider, so fpd = fvco / (N-divider * IncludedDiv). You may consider IncludedDiv as part of the N-divider, so whether it is =1 or other values does not affect sync category. 

  • 0 in reply to Noel Fung
    Prodigy 185 points

    Hi，

    Thanks again!

    But I have a little confused about SYNC mode. Could you please help me go through the SYNC procedure together?

    • Firstly, Because I want to use  RFoutB as SYSREF(4.8828125MHz)，VCO_PHASE_SYNC and SYSREF_EN must be set to 1, right?VCO_PHASE_SYNC =1 means IncludeDivider will be part of the N-divider as your said above.

    • Secondly,  RFoutA is used as VCO direct output(10GHz) ,  so channel divider in the RFoutA  path is bypassed that mean CHDIV after VCO is 1. 

    It meet the category1, and no uncertainty is introduced. The result is that RFoutA will always aligned with the reference clock(Fosc), right? 

    Actually, this situation like below figure. /N include IncludeDivider

    • Thirdly，RFoutB is used as SYSREF. My understanding is that IncludeDivider(=4) is included in feedback, but SYSREF_DIV_PRE+SYSREF_DIV+ Div2 are not. 

    my question is SYSREF_DIV_PRE+SYSREF_DIV+ Div2 will introduce phase uncertainty like /D2 in below figure, does it need SYNC mode to reset these divider？ 

    BTW， RFoutB is considered as which SYNC Category? 

    • Fourthly, Category1 seems to have two branch. The branch marked red circle is difficult to understand。SYNC mode required but No software/Pin SYNC pulse, so how to implement SYNC?

                 

    Best regards!!!

    Jason

  • 0 in reply to shen jie
    TI__Guru* 81580 points

    Hi Jason,

    SYSREF operation requires VCO_PHASE_SYNC = 1. As a result, SYSREF clock is synchronized with the RF clock.

    The upper Cat. 1 means VCO_PHASE_SYNC = 1 is required but there is no need to provide a SYNC signal to execute phase synchronization. 

  • 0 in reply to Noel Fung
    Prodigy 185 points

    Hi,

    For Cat.1, does no need to provide a SYNC mean RFoutA  have aligned with Foscin for LMX2594 ?

    If yes, RFoutA of these 4 LMX2594 will align with each other if edge of Foscin of them have been aligned at location of OSCinP/M pin? 

    Best regards!

    Jason