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LMK04828BEVM: PLL2 Does not Lock of LMK04828( PFD=160KHz and Loopbandwidth = 16 KHz)

ganesh singh1
Intellectual 400 points
Part Number: LMK04828BEVM


Hi ,

I am trying with LMK04828EVM only using PLL2 .

My OSCin  is 10 MHz and I want to generate 368.64 MHz LVPECL20 at output.

I am using PFD 160 KHz and Loop Bandwidth I modified to 16 KHz.  The PLL2 is not locking. 

Please help me in this regard. I am also attaching my config file in hex. I tried with both VCO present in PLL2

With Regards,

Ganesh Singh

LMK_AFE_10.tcs

LMK_AFE_10_Hvco.tcs

  • 0
    TI__Genius 12560 points

    Hi Ganesh,

    Your config files look good. Here, might be the issue is feeding external reference to LMK04828EVM.

    When you are feeding sine wave single ended signal at OSCin/CLKin, it should have higher amplitude (>10dBm) to meet the slew rate requirement of the device.

    Try with increasing 10MHz external sine wave input to 12dBm and see the performance. Your config files work well in my LMK04828EVM lab setup.

    Thanks!

    Regards,

    Ajeet Pal