LMK03328: Lock time

Hirotaka Matsumoto

Part Number: LMK03328

Hi all

Would you mind if we ask LMK03328?

We would like to confirm Lock time between loopband=10kHz and loopband=600kHz.
Could you refer to following figures;
■CH1=REF(External), CH2=OUT7, CH3=STAT0(LOCK)_LBW=10kHz, LockTime

■CH1=REF(External), CH2=OUT7, CH3=STAT0(LOCK)_LBW=600kHz, LockTime

We tried to confirm whether there is difference in case of each loopband setting.
However there is a little difference. Is it correct behavior?

Then, the datasheet shows "PLL to be locked and valid outputs are available" like as follows;

Above calculation, Txo, Tcal-pll and Tvco2 are the same value.
TLOCK-PLL2(PLL2 lock time) is ~4/LBW of PLL2.
-in case of LBW = 10kHz : 40us
-in case of LBW = 600kHz : 1.67us
On the figure, time range is 2ms, so lock time should incerase in case of LBW=10kHz.
Could you give us your opinion?

Kind regards,

Hirotaka Matsumoto

over 1 year ago

0 vicente flores prado over 1 year ago

TI__Genius 12711 points

Hi Hirotaka,

Did you change the external capacitor C2? A narrow LP BW would require an external C2 value of around 22uF whereas the larger LP BW would use a external C2 of 3300pF. I see identical plots above.

I am not entirely sure what you're asking here? PLL lock time is usually measured when device is at one frequency, say f1 and we program a new output frequency f2, the delay between f1 and the switch to f2 would be the lock time. PLL lock time is not measured by the delay between the reference signal being available and the output being seen.

Are you asking how long it takes the PLL to lock when reference becomes available or when the device has power applied?

Regards,

Vicente

0 Hirotaka Matsumoto over 1 year ago in reply to vicente flores prado

Guru 27525 points

Vicente san

Thank you for your reply.

Did you change the external capacitor C2?
->Yes, we mounted each capacitances like as following loop band setting. Except for C2, we configure setting of RC constants using registers.

<LoopBand=10kHz, C2=470nF>

<LoopBand=600kHz, C2=2.2nF>

Are you asking how long it takes the PLL to lock when reference becomes available or when the device has power applied?
->We would like to ask "when reference becomes available".
We assume that Lock time from when reference clock input becomes available is relation to loop band setting.
However there is no difference between LBW=10kHz and LBW=600kHz.
The datasheet shows TLOCK-PLL2(PLL2 lock time) is ~4/LBW of PLL2.
-in case of LBW = 10kHz : 40us
-in case of LBW = 600kHz : 1.67us

Kind regards,

Hirotaka Matsumoto

0 vicente flores prado over 1 year ago in reply to Hirotaka Matsumoto

TI__Genius 12711 points

Hi Hirotaka,
C2 must be changed as well.

Please refer to this past e2e post: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/664953/lmk03328-how-long-does-it-take-for-vco-calibration/2455195?tisearch=e2e-sitesearch&keymatch=LMK03328%20LOCK#2455195

Regards,

Vicente

Clock & timing

Clock & timing forum

LMK03328: Lock time