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LMX2694-EP: phase offset between outputs

Part Number: LMX2694-EP
Other Parts Discussed in Thread: LMX2594


We’re planning on using the LMX2694-EP in our RF design size of things and had a brief operational question.

The plan is to use both RFOUTA and RFOUTB outputs form the synthesizer to service two channels of an RF frequency converter.


It is clear to me that both outputs can be configured to the same output frequency inside the operating range of the synthesizer.


What is less clear to me is what the phase offset may be, if any, between these outputs.  At a high level it seems that any potential delay

may be due to just the differences between the physical Mux and Output buffer circuits that each output is subjected to.  These appear to be the same

based on the block diagram of datasheet page 14.


However a closer look at sheet 23 of the datasheet presents some additional circuitry that’s in place in the “B” path to support the SYSREF function

that’s not present in the “A” path.  I’m curious if this introduces some skew on the “B” output, relative to “A” even when configured for identical frequency

outputs.  Is there an offset that exists/could exist between the two?  If so, can you quantify how much?


  • Hi Adam,

    I don't have the LMX2694 board on hand, I tried this out with a LMX2594 board. At 7.5GHz output (= VCO frequency), I measured 6ps offset between RFoutA and RFoutB. This offset could be due to my scope, which is a 8GHz bandwidth scope. When I divided down the output to 625MHz, I cannot see any offset. 

    You should expect similar offset with LMX2694.

  • Hi Noel,

    Thanks for the help. 

    I have some additional questions that surfaced yesterday.  Has to do with the SYNC feature of the LMX2694 and family of RF Synths.


    I’m looking at the flowchart on Figure 7-5 of the datasheet to determine which category do my operational parameters

    fall under.  I’d like clarification on the diamond that calls out


                    fout % (2 x fosc) = 0


    The way that I understand it, the decision diamond asks whether the output frequency is integer related to twice the input reference frequency.

    I guess my specific question is whether this is asking for an integer relationship between the VCO output frequency, or the actual device output frequency?




    Fosc = 100MHz

    Fpfd = 200MHz (OSC_2X = 1)

    Fvco = 15000MHz

    Fout = 7500MHz (CHDIV = 2)


    If I follow the flowchart and evaluate true Fout (7500MHz) vs. 2xFosc (200MHz), the flowchart would put me in Category 4 where SYNC mode cannot be used reliably even though the PLL is operating in integer mode.  This because 7500MHz is not integer related to 200MHz.


    If I however compare the Vco output frequency (15000MHz) to 2xFosc (200MHz), those are indeed integer related and the flowchart pushes me to category 1b.


    Question 1: Can you clarify the above?  Which category does this example fall under?


    Question 2: What exactly is meant by the flowchart bullets under Category 1b?  Bullets state:

    • SYNC mode required
    • No software or pin SYNC pulse required


    Does this just mean that SYNC mode is required to be asserted in software (VCO_PHASE_SYNC = 1) during programming without any other action?  What’s throwing me off is the 2nd bullet of the Category 1b description.


  • Hi Adam,

    Whenever the following condition meet, we are in Cat. 4. 

    Channel divider is one of the sources that make trouble to synchronization, so the decision is made on RFout instead of VCO. 

    Cat. 1b means we have to set VCO_PHASE_SYNC = 1, but we don't need to provide an external SYNC signal to trigger synchronization. In other words, you can keep VCO_PHASE_SYNC = 1 all the time, no need to toggle it 0 - 1 - 0. 

  • Thanks Noel,

    a few more questions have come up on the LMX2694 regarding voltage sequencing and application of I/O.


    The application circuit on sheet 76 has adequately split the input voltage rails for digital power and RF power.


    In our application, we may have Vcc being powered first before the VccRF rail is enable to come up.  This could be

    Milliseconds of time. 

    1. Any issues with that?
    2. How about the SPI interface I/O.  Are these inputs cold sparable?  If not, what supply sequencing needs to be in place in order to avoid damaging conditions?  I.e., both VCC and VCCRF have to be up before applying SPI inputs?



  • Hi Adam,

    VccRF is used for the RF buffer, it should be fine to be up after Vcc.