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LMK1C1104: Parameters not specified in the datasheet

Part Number: LMK1C1104
Other Parts Discussed in Thread: CDCLVC1104,

Hi team

My customer is considering about replacing their current Renesas solution(ICS2304NZG-1LF) to ours, and is currently looking at LMK1C1104 and CDCLVC1104.

They will need some additional info to help making the decision, could you please help to fill the table below?




Input Capacitance


Output Capacitance



Cycle-to-Cycle Jitter



Jitter, 1-Sigma



Process Skew




  • Hi David,

    cycle to cycle jitter is typically not specified for buffers. Additive phase jitter is the common specification for noise.

    LMK1C1104 input capacitance is 7pF typical.

    We will look into the other parameters after thanksgiving.



  • Hi David,

    Below are some of the parameters that I was able to find for you.




    Typical input capacitance CIN_SE



    Maximum input capacitance CIN_SE


     7.9939 pF

    Maximum Additive Jitter at  (Include process variance)

    At 180 MHz

    VDD = 2.5, 350 fs 

    At 250 MHz

    VDD = 3.3V, 100 fs 

    At 156.25 MHz

    VDD = 1.8V, 20 fs 

    VDD = 2.5, 27 fs 

    VDD = 3.3V, 50 fs 

    Process Skew

    VDD = 2.5, 1150 ps

    VDD = 3.3V, 450 ps 

    VDD = 1.8V, 850 ps 

    VDD = 2.5, 350 ps

    VDD = 3.3V, 225 ps 

    For output capacitance, I would suggest to use IBIS models for both devices to estimate the VOH, VOL levels and rise/fall time etc. Because the behavior changes with trace and without trace for different capacitive loadings. It gets worse with trace length added with capacitive loading. 

    IBIS models:



    Let me know if you have any further questions.