LMX2594: why channel-to-channel skew of TIDA-01021 is <50ps

Hi Jason,

This board is not developed by our team, we do not know the details. 

Hi Jason,

The target analog CH-CH skew spec considered with the 90deg phase delay for 5200MHz (ADC12DJ5200RF) sampling clock, but that was validated using the ADC12DJ3200EVM on 2.7GHz clock. So you can neglect the target spec but the measured data are from the clocking board (< 10ps).

Thanks!

Regards,

Ajeet Pal

Hi Jason,

That's correct. For any fixed skew at the input of the multiple LMX2594, that will reflect at the output also after synchronization. The fixed skew at output can be aligned with the MASH SEED feature in LMX2594 and it will be deterministic over the power cycle.

For the JESD204B compliant clocks, if the skew between the sampling clock is fixed, using the SYSREF delay the system can have deterministic phase /skew and that can be correct in FPGA side.

If there is any fixed limitation on the skew, then the clock skew matters and need to be aligned/less skew.

Thanks!

Regards,

Ajeet Pal

Hi Jason,

shen jie said:

Q1. As you know, I have use external SYNC signal to align SYSREF out for these two LMX2594 as below figure shown. If I use MASH SEED to adjust slight mismatches in phase of RFOUTA out from two LMX2594 , will it impact the  procedure of SYSREF alignment  for two LMX2594? Or,  they are independent completely ?

For multi-device sync, first synchronize the LMX2594 using the SYNC input and later perform the SYSREF alignment to achieve the setup and hold timing requirement. SYSREF alignment will be to over the synchronized output.

shen jie said:

Q.2,  According to below figure shown and equation "Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN) × ( IncludedDivide / CHDIV )" ,

so Phase shift in degrees = 360 x (800/4000) x (4/1）= 288°@10GHz= 80ps, is it right?

To enable the MASH SEED, MASH order should be higher and the phase shift will be based on above calculation. PLL_DEN can be higher value and reduce the phase shift step size. I would be prefer to have small step size and can write multiple times to achieve the required phase shift.

shen jie said:

Q.3, When PLL_NUM or FRAC_NUM = 0, Which MASH order is reasonable?  It seems all order are OK as long as Min N divider and PFD_DLY_SEL are satisfied. I am confused very much by this ORDER selection

As mentioned above, MASH order should be reasonable (higher) and should meet the MASH order considerations.   

shen jie said:

1st item： PLL_NUM=0 is integer mode, so "MASH_ORDER must be great than zero" means I can't select integer mode in the MASH_ORDER field in TICS pro, right?  But, if I do, it won't appear any yellow warning or red error in TICS pro. 

2st item:  Is "For MASH_ORDER = 1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN"  contradictory with "For the phase adjust, the condition PLL_DEN > PLL_NUM + MASH_SEED must be satisfied" ?

MASH-order value can be selected based on Table 2. Where PFD_DLY_SEL and minimum N values are changed. For the same PLL_N (32) value, MASH-order-2 also valid and with PFD_DLY_SEL - 2.

Thanks!

Regards,
Ajeet Pal

Hi Jason,

shen jie said:

About Q1 in above post, I just want to know if external SYNC signal to align 4.8828125MHz SYSREF(RFOUTB) between two LMX2594 will collide with using MASH SEED to adjust slight mismatches in phase of  10GHz out(RFOUTA) between two LMX2594?  Maybe need sequence to ensure they can work independently, such as align SYSREF firstly with SYNC input, then align RFOUTA  with MASH_SEED function secondly?

As you are using the RFOUTA as VCO out, both LMX2594 outputs already synchronized (doesn't needed external SYNC). But the SYSREFout (RFoutB) would need SYNC input for alignment. Hence, the sequence would be first perform the sync with external sync input then provide the MASH_SEED for RFoutA clocks alignment Then later can provide the SYSREF delay in LMX2594 to meet setup and hold timing requirements.

shen jie said:

About Q2, Is IncludeDivider = 4 and CHDIV=1 in equation "Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN) × ( IncludedDivide / CHDIV )" according to below figure?  OK, I will increase PLL_DEN and write multiple times to achieve the required phase shift

You can choose the MASH_SEED value for required min. phase shift and then can write multiple times MASH_SEED value, not the PLL_DEN. Yes, can increase the PLL_DEN.

Thanks!

Regards,
Ajeet Pal