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LMK1D2102: Single-Ended Operation

Jejomar Ildefonso
Genius 9040 points
Part Number: LMK1D2102

Hi Team,

Our customer intends to drive the inputs of LMK1D2102 by a single ended LVCMOS signal. Figure 8-6 of the datasheet shows the needed bias voltage VTH = 0.5*(VIH + VIL) on the unused negative input.

However, it doesn't show any impedance requirements. Does it mean it is sufficient to have a resistor divider or to they need an op-amp to generate low impedance input? Seeking for your expert guidance.

Thanks in advance!


Kind Regards,

Jejomar

  • 0
    TI__Genius 10975 points

    Hello Jejomar,

    On the EVM document on our website, you can find how to set up your PCB for a single-ended LVCMOS input. The table below tells you how to design your board for proper configuration:

    You can then use the layout on p. 5 of the EVM to compare to that table and create your design.

  • 0 in reply to Andrea Vallenilla
    TI__Genius 9040 points

    Hi Andrea,

    Many thanks for looking into this! I just need some clarification about the configuration given on Table 6-1. If I remove R2, R4, R38 and replacing C1 and C7 with 0R, I have only the PU R5 on INN0 as there is no input signal on J3. Single Ended input will be on J1 - INP0. This would mean I have 1.8V on INN0 but expecting 0.9V.

    Did I get that right? Or am I missing some of the details?


    Kind Regards,

    Jejomar
  • +1 in reply to Jejomar Ildefonso
    TI__Genius 10975 points

    Hello Jejomar,

    You are correct, sorry about that. To go back to your original question, you can use a resistor divider to generate Vth from the figure below. In this case, only the input voltage matters.

    Good Luck,

    Andrea