LMK1D1204: IBIS Simulation for Input Side

Hi Jason,

Can you share your result with us? I will try to run this simulation and see if there is something wrong. 

Best,

Asim

When I look at the TDR impedance results I see this which I was not expecting:

Hi Jason, 

I am not able to run a simulation run due to licensing issues on my end for Hyperlynx. I will try to get it running by today. Meanwhile, can you confirm if you have any caps on VREF pin?

Best,

Asim

We do have a .1uF cap on the VREF pin.  Let me know if you have results. 

Hi Jason,

I have contacted design to take a look into this model. I will let you know of any update by Monday.

Best,

Asim

Hi Jason,

We simulated our IBIS model in cadence virtuoso environment. Our simulation had following test and parameter case. 

 ideal 50Ω driver, 5-inch t-line, ac coupled, 100MHz, 1nF AC cap, VREF ideal 1.2V source. In RLC case, a lumped 1nH/2pF cap.

We didn't those reflection as seen by you. 

VREF is not modeled in our IBIS model. So could you share more details about your simulation environment. 

1. How are they connecting our model? How is VREF modeled?
2. Do they see an issue with their LVDS driver into an ideal load with 50Ω/2pF cap?

Best,

Asim

Can you share the screenshot from your cadence virtuoso environment on the setup?  I want to see what the model looks like when you import and how you generate the 1.2V source.  

Hi Jason,

Here is environment setup.

Best,

Asim