LMK1C1106: clock signal integrity help

Hi Erik,

Can you also share the input waveform of the buffer as well. This seems like reflection coming from some mismatch and could you tell what are your trace capacitance. I want to replicate this issue.

Best,

Asim

I will scope the input waveform today.  Here is a transmission line calculator showing the particular characteristics of the transmission line:

Traces are anywhere between 3 and 7 inches in length.

And a screen shot of the layout route

Here is the input waveform of the buffer - there is large overshoot / ringing, should I use a series resistor on this line?

Hi Erik,

Are you trying to do level translation with this as well? Just curious or the input signal supposed to be around 1.8V LVCMOS. We can try the the series resistance to damp this waveform and see if the results improve. Meanwhile, could you send me all the other device operating conditions like supply voltage, loading etc. We will try to run a simulation and see if we can see the same problem.

Best,

Asim

No, FPGA is 1.8V and ADC is 1.8V.  We haven't looked at the supply voltage, I want to check that too as this is a new board that could have issues with power supplies.  Here is our schematic around the IC, do you think the ferrite bead (PN# MMZ1005A102ETD25) is too aggressive? 

HI Erik,

Ferrite bead depends what ripple frequencies we want to attenuate. This should be fine. Could you tell if the input overshoot damping helped? I will get back with simulation results and see if this problem can be replicated. Otherwise I have to order this EVM and check it on bench.

Best,

Asim

Hi Erik,

Can you check if Y4 to CH9 has the same issue which is not shared among two input of ADC? Also what is input specification of  ADC?

Best,

Asim

We are using the AD4630-24 for ADC.  The inputs are simply HiZ, single ended. Here is Y4 scope shot, looks better.  Any guidance on series resistors to try on other Y signals?

Hi Erik,

I think that could be coming from capacitive loading on those pin. I see that digital input of ADC have 2pF input capacitance. Trace capacitance would also be important. A general rule of thumb for FR4 material is around 2pF per inch of trace length. In the layout do you have two separate trace or just one and then it goes into two ADC? It looks like two separate traces after resistor so that would also contribute about 12 pF per trace.

You can double the pF loading on device based on trace length  if two ADC used. This could be causing this slowed down signal. 

Putting a series resistor would help at higher frequency with this distortion. We can start with a 10 ohm to avoid reducing the swing too much and keep it in acceptable range of ADC.  

Best,

Asim 

Hi Erik,

Let me know if this helped. I can close this thread then.

Best,

Asim

I have a pretty good SPICE model and series resistance doesn't seem to help.  The reflections dominate.  I'm thinking since the ADCs are close to each other, I can use one route and then bifurcate the route at the very end instead of bifurcating at the clock driver.  That way the signal only needs to propagate down mostly one route, instead of two.  In my simulations it seems to be working so I will try it next revision of our board.  thanks for your help, you can close.

Yes, I'm considering adding buffers to the board so that routes are not shared (each route is driven by one buffer output).  thank you