Can I input a 500mhz single ended clock if I reduce the voltage to less than 2V and bias the negative input to 1/2 the input range so it looks like a psudo differential?
The datasheet says single ended max input is only 250mhz. Buf If the negative input is bias to 1/2 Input would that put me in the LVDS input max range of 2Ghz?
Does the chip know the difference between a true LVDS vs a 1/2 biased LVCMOS input?
Will this work for this chip?