CDCLVP111-SP: cdclvp111-sp

chong kim

Part Number: CDCLVP111-SP
Other Parts Discussed in Thread: CDCLVP111,

According to the CDCLVP111-SP datasheet, the input differential voltage must be between 0.5V(min) and 1.3V(max). However, when a PECL driver is interfaced to CDCLVP111 in AC-coupled mode, the driver's output differential voltage nearly doubles at the input of CDCLVP111 violating the input voltage requirement. In other words, the driver output voltage (800mV) before the AC-coupled capacitors meets the CDCLVP111-SP input voltage requirement in DC-coupled mode, but not after the capacitors (in AC-coupled mode) which shows the differential input voltage of 0mV for logic 0 and 1.6V for logic high. Doesn't this (1.6V) violate the VID of 1.3V(max). Please advise.

Thanks.

over 2 years ago

0 Asim Khan over 2 years ago

TI__Genius 9250 points

Hi Chong,

After AC coupling the device. You would remove the DC offset from the output swing. VOD would stay the same. Specification of 0.5 to 1.3 V is for VID on the buffer.

For a LVPECL swing you would see the VOD swinging around 0V. So you would be have a swing from -400mV to 400 mV. If you measure this with a differential probe which would use the OUTN or OUTP as reference you would see a swing of 2*VOD on scope. That's peak to peak measurement. For CDCLVP111- SP that value is 2.6V so its under spec.

Please refer to below differential measurement method for reference. Let me know if this helps.

Best,

Asim

0 chong kim over 2 years ago in reply to Asim Khan

Prodigy 40 points

Thanks for the reply. Once the DC is removed, what I see is it swings +/-800mV around 0V at the input of CDCLVP111. So, Vid (|Vih - Vil|) is 1.6V which violates the maximum Vis of 1.3V. Correct?

0 Asim Khan over 2 years ago in reply to chong kim

TI__Genius 9250 points

Hi Chong,

What type prove are you using. It looks like you are using differential probe which would show this amplitude and its a Vss measurement as shown in above screenshot I shared. Its a peak to peak measurement so your actual VID would be VPP / 2.

Best,

Asim

0 chong kim over 2 years ago in reply to Asim Khan

Prodigy 40 points

I am doing this in simulation see below.

0 Asim Khan over 2 years ago in reply to chong kim

TI__Genius 9250 points

Hi Chong,

Use a smaller cap value or longer simulation time for it to settle to correct values.

This is not the exact simulation but you would see similar behavior.

Best,

Asim

0 chong kim over 2 years ago in reply to Asim Khan

Prodigy 40 points

I am still getting Vid > 1.3V even after a long simulation time.

0 Asim Khan over 2 years ago in reply to chong kim

TI__Genius 9250 points

Hi Chong,

Can you share your IBIS schematic with me?

Best,

Asim

0 chong kim over 2 years ago in reply to Asim Khan

Prodigy 40 points

All I want to confirm is that Vid (|Vih - Vil|) should be less than 1.3V as I am seeing more than 1.3V. I will deal with the model issue if necessary.

+1 Asim Khan over 2 years ago in reply to chong kim

TI__Genius 9250 points

Yes it should be less than 1.3 V around 800mV. You can double check your schematic and simulation environment.

Best.

Asim

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CDCLVP111-SP: cdclvp111-sp