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Original question:

LMK03318: The clock PLL is unstable

LMK03318: PLL unlock status in auto-switch event

wang shu
Prodigy 240 points
Part Number: LMK03318

Hello,

 1. Will the PLL unlock when the reference input is auto switched from secondary to primary in datasheet Figure.43?

 

The flowchart in Figure.44 describe that the PLL shall unlock momentarily when the mux auto switch to secondary input if the primary input is not valid. When primary input is valid, the mux auto switch to primary input, then PLL locked to primary input. Is there a short PLL unlock event happen before PLL lock to primary input?

I don’t see any PLL unlock event during the auto-switch process if the R51.2 is set to 1. So if the secondary input is aways available and R51.2 is 1. I don’t need warry about the PLL unlock event anymore, right?

2. In Table.8, number 14 status is “PLL secondary to primary switch in automatic mode”. what is it? Does the status pin generate a pulse after the mux auto switch to primary input? If yes, how long the pulse?

 

Regards,

 

  • 0
    TI__Genius 15040 points

    Wang,

    1. If the primary input is also valid, then there is no concern for glitches on the output due to reference switching. The reference must be within 2000 ppm of the secondary reference to be considered valid
    2. The status muxes can be set to one of these signals in the vitals table, but the mux can be disabled if this functionality is not desired.
      1. If it is desired, then the Status0 mux must be set to select the Status0 signal (R45[1:0] = 2), and then the Status0 signal must be set to PLL Secondary to Primary Switch in Automatic Mode (R27[7:4], polarity set by bit 3). When this condition occurs, this will set the Status 0 output high (or low, depending on the polarity bit). I will check to see whether this is for just the cycle when the switch occurs, or if this is latched.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 240 points

    Kadeem,

    1. We wish to use this PLL unlock status to reset our controller when the auto-switch event happen. But I feel if I set the R51.2=0, the controller shall be reset when the input switch from primary to secondary. There is a PLL unlock event. But the controller won’t be reset when the input switch from secondary to primary because there is no a PLL unlock event.

    If I set the R51.2=1, the controller shall not be reset no matter how the input switch, because there is no PLL unlock event during the switch process.

    If I am right, I prefer to use another status signal to reset our controller, not PLL unlock status.

    2. I wish to confirm whether this is a pulse signal when the switch occurs. We don’t want the controller is reset all the time because the status is latched after switch occurs. if it is a pulse, i prefer to use "PLL secondary to primeray switch in automatic mode" to reset my controller when the primary is valid again.

    Regards,

    Shu

  • 0 in reply to wang shu
    TI__Genius 15040 points

    Shu,

    I have an LMK03318EVM set up with the following reference clocks:

    • PRIREF: Single-ended LVCMOS clock at 25 MHz
    • SECREF: Differential XTAL at 25 MHz

    I perform the following steps:

    1. Configure the EVM so that PRIREF is output on Out4, SECREF is output on Out5, PLL is output on Out6 at 100 MHz.
    2. Set the Smart MUX up to automatically select the PLL reference input.
    3. Set the Status0 signal up to output on SEC-to-PRI switch
    4. Once PLL is locked, turn off the PRIREF source.
    5. Set scope to trigger on Status0 rising edge

    What I see is that when the primary reference is enabled, about 13 clock cycles pass before the status pin goes high. The status pin remains high for about 200 ns, then transitions to low and remains low. Additionally, the PLL output is not muted for about 1 ms after this occurs, except for during the Status pulse. 

    If you were to use this signal to reset, it will not trigger a reset when switching from PRIREF to SECREF, but it will reset when switching back from SECREF to PRIREF.

    If you set up the mute bypass, which should be done if you want the PLL output to continue during this condition, then the output is still active, although it drops from 100 MHz to between 92 MHz and 93 MHz.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 240 points

    Kadeem,

    Thank you. So the SEC-to-PRI switch will generate a 200ns pulse. I could use it as reset_n signal if I convert the polarity.

    “Additionally, the PLL output is not muted for about 1 ms after this occurs, except for during the Status pulse.” What this mean, the PLL unlocked during the status pulse? If the PLL clock drop to 92MHz, i think it is unlocked, am i right?

    Regards,

    Shu

  • 0 in reply to wang shu
    TI__Genius 15040 points

    Shu,

    I believe that you are correct here. 
    Let me correct my wording from earlier. If the output is muted during the switch event, then the output clock is disabled for about 1 ms when this switch occurs, except for while the Status0 signal is high.

    If the mute is bypassed (as is specified in the datasheet), then it looks like the PLL is locked to a lower frequency (it is at 92 MHz, but constant), before returning to 100 MHz after about 1 ms.

    Thanks,

    Kadeem