LMK1D1208: LVPECL input termination

Hi Mikko,

To my knowledge, the chip does not have any built-in mechanisms for LVPECL termination and AC-coupled LVPECL is not strictly required. I think the standard DC-coupled LVPECL termination (from this E2E blog post) would be a good place to start:

In other words, assuming you are using 50 Ohm traces, place 50 Ohm termination resistors shunted to (VDD - 2) Volts just before the device LVPECL input pins. In the event that you do not have a (VDD - 2) Volt node available in your design, you can use a Thevenin equivalent in the form of resistor voltage dividers.

However there is one potentially important detail I want to check with my team: I see that the AC-coupled LEVPCL input scheme in the datasheet has 75 Ohm series resistors that are "required to reduce the LVPECL signal swing if the signal swing is >1.6 Vpp", and there are no series resistors in this standard DC-coupled LVPECL termination. I will confirm if they are required for DC coupling or not and let you know shortly.

Thanks,

Evan Su

Hey,

Any news for this termination issue?

If LKM1D1208 input stage is supporting standard LVPECL I could make termination as picture shown below (Input stage VDD=2.5V):

How about termination would be if LKM1D1208 VDD is 1V8 or 3V3?

Or is it mandatory power LKM1D1208 from 3V3 since driver is 3V3 LVPECL? 

It seems that LKM1D1208 Vinp-p is 0.3...2.4V (see data below). Barely ok with DC-coupled LVPECL (T-termination, voltage swing 1.6...2.4V)

Hi Mikko,

Sorry for the delay. The series resistors are fundamentally there to reduce signal swing to a level that the receiver can tolerate, so they should still be included in the DC-coupled LVPECL termination if that problem still exists.

To my knowledge, different values of VDD can affect termination if the Thevenin equivalents are used, because the resistor values must be different to achieve an equivalent node of (VDD - 2) V. I am not familiar with how to interface a LVPECL driver and receiver operating at different supply voltages, intuitively I would assume that as long as the receiver can accept the input specifications (peak-to-peak, common mode voltage, etc.) then it should be fine. I'll ask around to see if there are any special considerations.

Thanks,

Evan Su

Is there any employees at TI who have facts for questions above?

Hi Mikko,

What is the supply voltage and VOD of the LVPECL driver? What supply voltage you want to apply to LMK1D1208? These information will help me figure out the DC-coupling schematic for you.

Hi Noel,

Drived is standard 3.3V LVPECL as written in the 1st post.

VDD and VOD: 3.3V

Preferred VDD for LMK1D1208 is 1.8V but if some reason this is not possible then 2.5V and 3.3V is also ok.

Are datasheet Vin,diff and Vicm correct for (VDD=1.8V)?

Clock input pins can be up to 2.9V (2.3V + 0.6V)?

Hi Mikko,

In order, to determine if your driver can be directly DC-coupled to the LMK1Dx input, please clarify these details:

• What is your LVPECL driver common-mode voltage?
• What is the driver's swing spec?
• What is the driver's VOH and VOL levels?

The alternative is to simply AC-couple the input. The LMK1Dx has the VAC_REF pin which provides the biasing voltage.

As Evan mentioned, depending on your LVPECL swing, the series resistor will be 0 or 75 ohms.

Regards,

Jennifer

The driver is ADCLK948 and its output characteristics can be found below,

Datasheet if some more details is needed,

www.analog.com/.../ADCLK948.pdf

Noel, you replied "I think" Is there some one at TI who knows facts? 

Is there an error in the datasheet regarding Vicm values?

Is termimation ok for LMK1D1208 (all VDD, 1V8, 2V5, 3V3)? 

Voltage in IN0 pins will be look like with termination (see picture above):