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LMK5C33216: Phase reliability info

Part Number: LMK5C33216

Hi team,

For a new project, I want to explore the possibility of using your LMK5C33216 device as a SYSREF and reference clock generetor for radio modules.

I need to make a synchronization network between 4 modules connected on paths that are due to a previous implementation (old backplane) , so I can't make a star clock distribution path.

Two main requirements must be met:
1) The system must guarantee phase coherence at each restart (or rather, all the outputs must restart with a known phase between the modules outputs).

I plan to do this feature using ZDM with a 3.84MHz SYSREF signal between modules).
Using the configuration shown in the attached diagram, do you think it is possible to obtain phase certainty between the modules which is comparable to the output skew between a single LMK5C33216 device?

2) The main device (MODULE 1, system primary clock source) must be able to tune the frequency of all the system outputs (4 modules) by acting on its own DCO.

Do you think there are any impediments?


  • Hi Massimo,

    We have paged a device expert to assist you. To be clear, is the 3.84 MHz SYSREF signal being daisy chained through the LMK5C33216 devices?


    Evan Su

  • Hi Even, Yes two levels of daisy chain

  • Hi Massimo,

    Thanks for the information. As I understand the zero-delay mode can be configured with almost perfect alignment between input and output, so I think the reference seen by Module 4 should be closely phase-aligned with the reference of Module 1. There would be some latency between the outputs due to the different signal path lengths, but using delay compensation could help if that is a problem. Hopefully our device expert can get to you next week to confirm, if he is still busy I can try to loop in our DPLL systems expert.


    Evan Su

  • Hi Massimo,

    I see what I presume are your pairs of device clock + SYSREF to each of the four radio modules.

    Just to confirm,

    1. for your JESD204B - are you needing the SYSREF edges to assert at the exact same moment deterministically?  Or,
    2. is it acceptable to have the SYSREF to deterministically synchronize the device clock with respect to the SYSREF?
      • Meaning, the LMFC will be synchronized deterministically between all radio modules, but the LMFC synchronization may have happened at different times (but on a SYSREF period edge).
      • This option makes it quite simple to run the 3.84 MHz in zero delay mode (ZDM) and then you can request SYNC without any timing requirements.

    Side note, higher XO frequencies like 48 MHz can result in improved jitter.  Is there a reason you have chosen 16 MHz?