Not part number

If your own DPLL is implemented in an FPGA, it's likely simpler to just implement a second DPLL to lock the external reference to the OCXO, extract the filtered TDC measurements, and scale them (possibly with voltage/temperature corrections) to the code of a high-precision DAC driving the control port of the OCXO. This preserves your ability to enter holdover or to DCO the OCXO with voltage/temperature corrections independent of the frequency lock, costs less than a separate auxiliary PLL, and takes up less board area. I'm a clocking support engineer so I don't know the DAC portfolio well, but by inspection, something like DACx0502 seems small, cheap, and decently accurate (2.5x2.5mm, ±1 LSB DNL/INL, $4 | 1ku). I could get someone from the DAC team to comment if the DPLL + DAC approach sounds better, as they may have a better recommendation for you.

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As a clocking support engineer, I'm qualified to recommend some PLL-based solutions. I'll preface this answer by saying I don't think we have a simple, drop-in solution for what you need in our PLL portfolio. I have some suggested approaches, but you may have better luck finding a device with a basic holdover PLL at another vendor.

We have two approaches, analog and digital, for implementing a holdover function that maintains the setpoint frequency in the absence of a reference. Assume that you have buffered your external 10MHz signal to both your VCXO DPLL and your OCXO PLL.

The analog approach uses an analog PLL such as PLL1 from LMK04228. Your external 10MHz drives the reference to the PLL, and the OCXO drives the feedback; the control voltage is connected to the charge pump and loop filter node. The LMK04228 offers a programmable holdover tuning word that can manually set the output voltage of the charge pump in the holdover condition, which could be used for initial programming. When the external 10MHz reference is present, the OCXO is locked to it, and the PLL begins sampling the charge pump voltage to record a holdover tuning word. If the external 10MHz fails, on-board loss-of-signal detection or loss-of-lock detection, or even pin control if external failure detection is available, will cause PLL1 to enter holdover, using the new tuning word to keep the OCXO nominally on-lock.

This scheme has several advantages:

• Relatively simple
• Consumes little power
• Requires little to no user intervention beyond initial programming

However, there are several drawbacks:

• LMK04228 PLL1 phase noise is likely worse than a 10MHz OCXO; at low bandwidth you'd need big caps and you'd still get considerable 1/f noise
• LMK04228 is a 64-pin dual cascaded PLL with 14 outputs, and you'd be paying for all of it while powering most of it off
• Holdover precision is only 10-bit across 3.3V range, depends on supply voltage, and may not have great INL

The digital approach uses a fractional digital PLL such as LMK5C33216 to adjust around any frequency error in the OCXO, rather than tuning the control port voltage. The OCXO is used as a reference to a fractional analog PLL with a high-frequency, low-noise BAW resonator as the VCO. The feedback path is also sampled to a DPLL which attempts to lock to an external signal. Error in the DPLL accumulates as a tuning adjustment at the fractional divider of the APLL, slightly modifying the VCO voltage. The DPLL can take an initial holdover coefficient to tune out expected OCXO frequency error, and has an accumulated history function that preserves the frequency output of the PLL in holdover once a reference has been applied.

This scheme has several advantages over the analog variant:

• Tuning word for holdover has sub-femtosecond average precision
• Control port for OCXO can be tied to a stable DC reference or GND, eliminating voltage coefficient in manual characterization
• DPLL can act as a DCO for the OCXO in holdover, allowing pure digital tempco compensation (with an external temperature sensor)

But it also suffers some of the same drawbacks, and a few new ones:

• No direct OCXO output - must go through a PLL, which limits phase noise to performance of BAW and fractional PLL
• Need a BAW VCO that isn't an integer multiple of 10MHz to avoid extreme integer boundary spurs - only one such device available (LMK5C33216)
• LMK5C33216 has three DPLLs, three APLLs, and 16 outputs; again, paying for all of it while powering most of it off

Any other solutions I could propose would be variations on that common theme. Again, let me know if I should get someone from DAC team to weigh in.