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Part Number: LMX2582


We are facing issue regarding the lock detect of the LMX2582.

The lock detect indicate that the PLL is in lock state even if its not (the output frequency is incorrect).

What we can do in order to solve that issue?



  • Hi Ronel,

    Please provide your register configuration. What is your input clock frequency and format?

  • The input CLK is provided by 50Mhz VCTCXO reference, part number - LFVCXO066860Bulk. 

    I want to mention, when the PLL is in lock state, it provided good PN performance -51dBc integrated from 1Khz to 100MHz. 

    The configuration is:

    R70 0x460000
    R69 0x450000
    R68 0x440489
    R64 0x400377
    R62 0x3E0000
    R61 0x3D0000
    R59 0x3B0000
    R48 0x3003FC
    R47 0x2F08C0
    R46 0x2E1FA3
    R45 0x2D0003
    R44 0x2C0000
    R43 0x2B000B
    R42 0x2A0000
    R41 0x29000A
    R40 0x280000
    R39 0x278204
    R38 0x260024
    R37 0x254000
    R36 0x240811
    R35 0x23021B
    R34 0x22C3EA
    R33 0x212A0A
    R32 0x20210A
    R31 0x1F0401
    R30 0x1E00F4
    R29 0x1D0084
    R28 0x1C2924
    R25 0x190000
    R24 0x180509
    R23 0x17B042
    R22 0x162300
    R20 0x14012C
    R19 0x130965
    R14 0x0E0FFC
    R13 0x0D4000
    R12 0x0C7001
    R11 0x0B0018
    R10 0x0A10D8
    R9 0x090B02
    R8 0x081084
    R7 0x0728B2
    R4 0x041943
    R2 0x020500
    R1 0x01080A
    R0 0x00221C

  • Hi Ronel,

    Please set LD_TYPE = 1, this setting will check Vtune voltage to ensure it is indeed locked.

  • Thanks!

    Now its working indeed. 

    We disconnected the loop filter and now the LD indicates that the PLL is not in a locked state - so its working.