• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 349 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE8030EVM: Data Path Latency for TX of AFE8030

Shiva Pinagani
Prodigy 60 points
Part Number: AFE8030EVM
Other Parts Discussed in Thread: AFE8030

Hi Team,

As we are Testing the data path latency from FPGA to TI we have seen very high latency of ~740ns.The test procedure as follows 

So we are Triggering the Signal from the Intel board and at the same time we are triggering the VSA trigger input so we see the Latency of ~740 ns form FPGA to TI .

and we also tested with oscilloscope also we have experience the same result of ~740ns is it the expected Behaviour of TI AFE8030. are we testing it correctly ?

and also we are facing the Problem on SPI transaction for single transaction  with 10Mhz SPI clock we are getting ~96us Latency . what is the Maximum clock we can give to TI board ? 

  • 0
    Prodigy 60 points

    Hi team 

    As we got this from the AFE8030 Document .

    our settings are 

    • LMFSHd = 1-4-8-1-16 , 7864.32 MSPS , interpolation 32x
    we are getting very high as ~740ns with our settings
  • 0 in reply to Shiva Pinagani
    TI__Guru 69594 points

    Hi Shiva,

    Ben will be looking into this. Usually, when the interpolation stages go up, the latency number will increase.

    Please advise how the trigger signal from the FPGA is generated? We will need to know if this trigger signal is aligned with the data pattern generation of your JESD204 TX block.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 60 points

    Hi Kang,

    This is the how the Trigger Signal is aligned to JESD TX

    -Shiva

  • 0 in reply to Shiva Pinagani
    TI__Intellectual 2685 points

    Shiva,

    We have the ability to create a similar trigger in our TSW14J58 FPGA EVM. I have replicated your system parameters with 245.76MSPS interface rate and confirm a delay time of approximately 730 ns on my setup.

    The delay time between AFE JESD interface and AFE TX output is dependent on the interface rate to the DUC inside the AFE80xx. From the datasheet snippet you posted, you can see that as interface rate is decreased from 737.28 MSPS to 491.52 MSPS, the nominal latency increases from 295 ns to 440 ns.

    Regards,

    Ben Uhing

  • 0 in reply to Benjamin Uhing
    Prodigy 60 points

    Hi Kang ,


    Thanks for this result. Can you help us with the Rx side latency also? we are thinking about the similar setup with VSA(Vector signal generator ) Our Rx settings are as follows - 

    • LMFSHd = 1-4-8-1-16 , 3932.16 MSPS, interpolation 16x


    Also can you tell us a procedure that we can follow to test the Rx side latency?

    Regards,

    Shiva

  • 0 in reply to Shiva Pinagani
    TI__Intellectual 2685 points

    Shiva,

    I have a possible test procedure proposal, but we have not verified this at TI yet.

    On your FPGA/ASIC, create a trigger signal. Align this trigger signal's rising edge with the start of the ADC capture at your FPGA/ASIC.

    Feed this trigger signal into an AFE GPIO signal defined as  a NCO switch input. This input will be used to switch the AFE TX channel from NCO 0 to NCO1

    Transmit a pattern from the AFE TX centered at NCO 0 and loop back this signal into AFE RX

    Start capture on your FPGA/ASIC and send trigger signal

    The trigger signal will cause the TX NCO to change to NCO 1

    Look at the captured signal from AFE RX. There will be some data centered at NCO 0 and then a transition to NCO1.

    The delay between trigger and NCO transition will be the sum of (TX NCO switch time) + (AFE RX capture delay)

    We have data on TX NCO switch time which can be subtracted from your total latency to determine the AFE RX capture delay.

    What do you think of this proposal?

    Regards,

    Ben Uhing