• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 23 subscribers
  • Views 518 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCI6214: PLL unlock

William Zhang2
Intellectual 905 points
Part Number: CDCI6214

Hi Team,

This is technical support request for CDCI624. When CDCI6214 PLL unlock occurs, except for powering off and restarting, no matter how you configure the chip or RESET, it cannot return to normal. After merging the i2c of the CDCI6214 EVM development board into the chip and configuring it, the phenomenon remains the same. At this time, except for Y0 which can output normally, the other channels cannot output normally if different configurations are selected.

When used CDCI624 for PLL parameter calculate, we selected custom since there is no CDCI624 option in PLLatinumSimm for device selection. Is that correct like below picture shown?

The Phase-Locked loop Circuit in below picture is not the similar with the CDCI624 internal, is it will unavailable?

William

  • 0
    TI__Mastermind 19820 points

    William,
    We offer some guidance for selecting the loop filter values based on common use cases in both the datasheet and TICS Pro - see below:

    Is the RESETN/SYNC pin configured as an output synchronization pin? Is this pin pulled high or low? If low, then the outputs will be muted until the pin is pulled high:

    Are GPIO1 or GPIO4 configured as output enables? Are the individual mute bits set for any of these channels? Is the lock_det (R7[0]) bit a '1', indicating that the PLL is locked to the reference? Y0 will output regardless of the lock state of the PLL, as it is a bypass.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Intellectual 270 points

    Hi,pin configuration is this , controled by MCU.  

     

    our vco freq is 2673MHz .

      

      The pll unlock Problem, We suspect it's the RC parameter.   Because there are no parameters for 2673MHz 

  • 0 in reply to user4978070
    TI__Mastermind 19820 points

    Hello,

    We recommend using the closest VCO frequency loop filter for this application: 2680 MHz or 2688 MHz VCO. The choice between the three depends on your phase detector frequency and desired bandwidth.

    The pole is set by the pll_lf_pcap value, and the zero is set by the pll_lf_zcap and pll_lf_res values. Using the custom device on PLLatinum Sim is suitable here to estimate loop filter parameters.

    Are you recalibrating the PLL (the Re-CAL button) after changing parameters? This should be done in order to recalibrate the PLL to achieve lock.

    Thanks,

    Kadeem