CDCI6214: It cannot generate expected clocks

wang shu

Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214

Hi,

I wish to generate 2MHz clocks from channel 2 and 3. But the measured output clocks are always 760KHz. The input is 80MHz LVDS ac-coupled input.

Below figure is block diagram in TISC Pro. The input is bypassed to Y0. I can measure an 80MHz clock. So I don’t know why the outputs are 760KHz. The PLL is unlocked, but I tried several options, on one can lock it.

TICS Pro

80MHz output at Y0

760KHz output

over 1 year ago

+1 wang shu over 1 year ago

Intellectual 260 points

Hi,

I sloved it. I tried more options to set the PLL to lock. now it can generate 2MHz clock.

Regards

0 Kadeem Samuel over 1 year ago in reply to wang shu

TI__Genius 16640 points

Wang,

I would like to note - we recommend using the CDCE6214 over the CDCI6214 for any new applications.

Thanks,

Kadeem

0 wang shu over 1 year ago in reply to Kadeem Samuel

Intellectual 260 points

Hi Kadeem,

why CDCE6214 is more better for new application.

we do care about the jitter very much. CDCI6214 jitter is better than CDCE, right?

Regards,
Shu

0 Kadeem Samuel over 1 year ago in reply to wang shu

TI__Genius 16640 points

Wang,

The CDCE6214 has more functionality, including a fractional PLL, with slightly better jitter performance.

Thanks,

Kadeem

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CDCI6214: It cannot generate expected clocks