Hi Team,
This is FAE Jayden, my customer uses LMX2541SQE3030E/NOPB in their system. The customer found that the rising edge/falling edge of the 1GHz sine clock signal output by the FPGA configuration was not ideal (see the test waveform) and needed help troubleshooting the problem.
The schematic and the test waveforms are as below:
1. To get a more ideal sinusoidal clock signal output, can it be improved through SPI configuration parameters? Or are there any improvements in the hardware like PCB? Is there any relevant information for the specific SPI configuration that can be provided to the customer’s FPGA engineers for reference?
2. Can we provide relevant testing guidance regarding the phase noise indicator test of clock signals?
Look forward to your reply! Thanks.
Jayden
