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CDCI6214: Custom loop filter settings and simulation

Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214


we are deploying the CDCI6214 clock generator on a new generation of our measurement hardware. The datasheet claims that the CDCI6214 features configurable loop bandwidth between 100kHz and 3MHz. We would like to get as close as possible to the 100kHz bandwidth.

Unfortunately, the presets defined in the datasheet and in the TICSPRO software do not cover this case at all, regardless of REF/VCO frequency. In addition, the CDCI6214 is not in the device list of the PLLATINUM-SIM simulation software.

Can you please tell me how we can simulate the loop filter to find appropriate settings for bandwidth closer to 100kHz for our applications?

Best regards,

Henning Heggen

  • Henning,

    The CDCI is NRND, we recommend switching to the CDCE6214 for new projects.

    The loop bandwidth and the phase-frequency detector frequency are related. From Table 2 in the datasheet, with the charge pump current, Cpcap, Rres, and Czcap held constant, reducing Fpfd from 50 MHz to 25 MHz reduces the loop bandwidth from 0.97 MHz to 0.51 MHz.

    Reduce the PFD frequency (and increase the n divider of the PLL) in order to reduce the loop filter bandwidth.

    Decreasing the charge pump current will also reduce the loop bandwidth.

    Note that this reduction in the loop filter bandwidth may lead to increased output clock jitter.


  • Kadeem,

    Thank you for your recommendation and the provided information about the loop filter bandwidth.