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CDCE6214-Q1: Pin Mode for the CDCE6214-Q1

John Oliver
Prodigy 10 points
Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCE6214,
I'm trying to design in your CDCE6214 PCIe Clock Generator and have some questions. Can you help?
First Issue:
I'm trying to design a test backplane for some PCIe cards. I have three x8 slots, each needing a 100MHz reference clock. I'm trying to design the CDCE6214 and run it in "Pin Mode", but I can't figure out how to ensure that I've strapped the I/O properly to ensure that it is indeed in "Pin Mode". I want to drive out three 100MHz PCIe reference clocks; OUT1, OUT2, and OUT3. I don't need OUT1, and am wanting to use the GPIO pins to enable OUT1 through 3 while disabling OUT4. 
I just want to have it soldered on and "it just works". No I2C bus, not messing with the registers. I see how to enable the I2C bus, but nothing in the datasheet seems to specifically say how to enable the GPIO pins to act as enable pins for the Clock Outs. Can somebody look at my schematic (attached below) and tell me if it is configured properly?
 
Second Issue:
Figure 35 in the datasheet shows stronger pull-ups and pull-downs of 4.7k ohms. But the body of the datasheet says to use 50k ohms. Which should I use?
Third Issue:
The symbol that I downloaded from Mouser (which I believe they got from you) shows four pins named A1, A2, A3, and A4. Nothing is mentioned about these pins in the datasheet. What am I supposed to do with these four pins?
 
Fourth Issue:
Again, I don't want to have to program any registers. Because of the "HW_SW_CTRL" pin, I can see how to select I2C, EEPROM Page 0, or EEPROM Page 1. Because I don't want to use I2C, I currently have it set up by selecting EEPROM Page 0. But what is in/on the EEPROM Base Page? Does the EEPROM Base Page have default register settings? Does the EEPROM Page 0 have default register settings? Which EEPROM page should I be using if I don't want to mess with the registers? Am I going to need to pre-program the EEPROM before I can mount this device onto my board?
Any help is greatly appreciated.
  • 0
    TI__Mastermind 21200 points

    John,

    1. First Issue:
      1. Does your XTAL require capacitors to GND? Or is the plan to use the internal capacitors only? The CDCE6214-Q1 has internal load capacitors ranging from 3.0 pF (default) to 9.0 pF.
      2. Use ferrite beads to isolate the 3.3 V supplies of the different supply rails. This will reduce noise on the output clocks.
      3. The best practice is to add series 0-Ohm resistors for the PCIe clocks near the device. These can be adjusted in the evaluation stage as needed for impedance matching.
      4. Connect the REFSEL pin to GND through a resistor for always selecting the SECREF pins as the reference to the PLL.
    2. Second Issue:
      1. The internal resistors on these pins are 50k. Using either 50k or 4.7k resistors is suitable
    3. Third Issue:
      1. These pins are for mounting purposes only. These pins can be floating or connected to GND
    4. Fourth Issue:
      1. The fall-back mode page serves as a means of having I2C access if both EEPROM pages are configured for pin mode. The registers on this page are always consistent at startup and cannot be reprogrammed. This page can be used for programming the other EEPROM pages. This is the "EVM Default" configuration in TICS Pro. Both EEPROM pages are configured for 100-MHz LP-HCSL output clocks on OUT1 through OUT4 from a 25-MHz XTAL input on SECREF (the datasheet says LVDS on page 40, this is incorrect and is being updated). For pin mode, use EEPROM Page 0. The GPIO pins are preconfigured for individual output enable control on this page.

        I recommend having a means of accessing the I2C pins in the event that a change is required to the EEPROM. This way the fall-back mode page can be accessed by leaving the REFSEL and HW_SW_CTRL pins floating.

    Thanks,

    Kadeem

  • +1 in reply to Kadeem Samuel
    Prodigy 10 points

    First Issue: 

    a. I totally forgot to ask about this.  I hooked up the crystal like I saw in Figure 35 of the Datasheet not knowing what was going on inside your chip ... and I was going to ask about that.  Good catch.  So am I O.K. using fewer parts on my board, or do people typically put caps on each side of the crystal?  What do you recommend?

    b. Another good catch with the ferrite beads.  The Datasheet said that the most the entire part would consume was under 100mA.  So I put a 100mA bead on each input thinking that would be safe.  Thoughts?

    c. Another EXCELENT suggestion.  Done.  (Thank you!)

    d. DOPE!  I TOTALLY spaced that off.  Would have been really embarrassing.  Thank you, thank you, thank you!

    Second Issue:

    a. Thank you.  I'll just leave the 50k in there and hope that they are not too weak.

    Third Issue:

    a. Thank you.

    Fourth Issue:

    a. I guess I could de-Pop Resistors R5, R6 for the I2C and pull resistors R19 and R8.  So thank you for that.

    Here is my updated schematic ... what do you think?

  • 0 in reply to John Oliver
    TI__Mastermind 21200 points

    John,

    1. First Issue:
      1. It would be best to add the footprints for the two capacitors to GND. Some XTALs require more load capacitance than 9 pF, which would necessitate the external capacitors.
      2. The max Idd for 4x 100 MHz LP-HCSL outputs is 90 mA. It would be best to use a ferrite bead with a larger current rating. An example of this would be BLM15AG221SN1D, which is rated for 450 mA.

    The schematic looks much better.

    Thanks,

    Kadeem