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CDCLVP1102: Recommended Design for CDCLVP1102

Part Number: CDCLVP1102

Hi Teams,

Happy new year for 2024!

My customer is considering CDCLVP1102 and has some questions need to answer:

1. Can you provide the recommended application schematic diagram? 

2.Customers need two outputs to reach the device at the same time. What is the delay time between the two output channels?

3. Are there any similar automotive grade chips that you can recommend? Sample time and mass production time?

Thanks!

  • Guohai Lin,

    1. Section 6 of the EVM user guide shows the EVM schematic and can be a good place to start. Section 9.1 in the datasheet also provides more information on typical applications.  

    2. The delay time between the two output channels, which TI calls "output skew" for the CDCLVP1102 is 10 ps.  If you truly need outputs with 0 output skew, there are more complex clock generators which have output delay functionality that can produce outputs that are totally in phase and have no perceived skew.

    3. We do not currently offer any automotive LVPECL clock buffers. But, if you do not require LVPECL then, there are 4-output LVCMOS and HCSL Automotive grade clock buffers. The LMK00804B-Q1 and LMK00334-Q1 respectively.  

    Regards,

    Will

  • Hi Will,

    Thanks for your answer.

    Does CDCLVP1102  not support LVDS output? Is there any recommendation for a 1:2 buffer that supports LVDS output?

  • Guohai Lin,

    The CDCLVP1102 is a universal input, LVPECL output buffer.  We do not offer any 1:2 buffers that have LVDS outputs.  But the LMK1D2102 is a dual 1:2 LVDS buffer and the LMK00304 is a 1:4 buffer which can be configured as an LVDS output.  With both of these devices you can use them functionally as a 1:2 LVDS buffer, powering down the unused output banks.

    Happy New Year, and let me know if you have any further questions,

    Will