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LMK03328: Loss of Lock Readback Register

Part Number: LMK03328

I am in the process of verifying the operation of an LMK03328 Clock device where is it relying on the secondary input input clock that is being used to drive PLL2.   

I want to verify that the PLL2 is locked by reading registers on the LMK Device (I do not have access to the STATUS0/1 pins.)

Is reading the LIVE_INT (reg 13) that best way of getting this status?  (LOL2 and LOS2 bits.)
Is there anything that needs to be done special to clear the status of the register when an error is set or cleared?

If I do not see the conditions clear, what is the best way to reset the device.


Doug Bailey

  • Hello,

    The clock gen team is out of office until Tuesday 1/16. Please expect a delay in response and thank you for your patience.

  • Doug,

    The LOS2 bit can be used to tell if the reference signal has been lost or does not have enough voltage swing to be used. This assumes that the reference had these correct conditions when the device was powered on. If the device is powered on with no reference, then the LOS2 bit will not be activated. Rereading LIVE_INT will refresh the status.

    LIVE_INT is not reliable for detecting LOS2. STATUS0/1 is best for that. 

    When R17[0] is 1, R16 can be used for LOL detection, just be aware that these are sticky bits and will remain 1 until they are manually cleared, regardless of if the issue is resolved.

    The best way to reset the device is to perform a power cycle, however toggling RESETN_SW R12[7] is another way to reset the device.