LMK00105: Fixed output, Power sequency requirement

Taketo Sato

Genius 9975 points

Part Number: LMK00105

Hello team,

I have questions about LMK00105 below. Could you answer below?

Can I expect output to be fixed logic Low if we we force OSCin to be fixed logic High and input SEL selects OSCin?
Does the device have power sequence requirement between Vdd and Vddo?

Best regards,

10 months ago

0 Andrea Vallenilla 10 months ago

TI__Genius 10975 points

Hello Taketo,

I'll get back to you by next week.

Best,

Andrea

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

Thank you for your support. I wait for your prompt confirmation.

Best regards,

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

Could you please support about this LMK00105?

Best regards,

0 Andrea Vallenilla 10 months ago in reply to Taketo Sato

TI__Genius 10975 points

Hello Taketo-san,

Taketo Sato said:
Can I expect output to be fixed logic Low if we we force OSCin to be fixed logic High and input SEL selects OSCin?

That is correct while crystal mode is selected and no AC signal is applied to OSCin, as explained in p. 10 of data sheet:

Taketo Sato said:
Does the device have power sequence requirement between Vdd and Vddo?

There should not be a specific power sequence. Are you asking to double check there's not one or are you seeing any weird behaviors in the process? Also, thought I add the snapshot from p. 9 of the data sheet about further info on Vdd and Vddo if interested. Please pay careful attention to the note:

Best,

Andrea

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

Thanks for your comment.

There is no power sequence requirement statement in datasheet but Vddo before Vdd may cause damage on internal ESD structure so Vdd before Vddo, or Vdd, Vddo power up same time is typically recommended to avoid the NOTE description, correct?

Best regards,

0 Andrea Vallenilla 10 months ago in reply to Taketo Sato

TI__Genius 10975 points

Hello Taketo,

Datasheet is NOT saying that Vddo needs to be powered up before Vdd. Data sheet is saying that the Vddo voltage (not order that the Vddo/Vdd are turned on) has to be lower than Vdd voltage. So whether Vdd or Vddo is powered first, there should not be a effect on the ESD structure.

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

Thank you for the comment. Sorry but let me ask again for power sequence for double check.

Andrea Vallenilla said:
So whether Vdd or Vddo is powered first, there should not be a effect on the ESD structure.

Vddo is powered first then it will create a condition of higher Vddo voltage than Vdd voltage until Vdd is powered. With the NOTE description I imagine that there is protection diode between Vddo and Vdd. And if there is a condition of Vddo > Vdd+0.3V the protection diode may be damaged. Is my understanding wrong?

Best regards,

0 Andrea Vallenilla 10 months ago in reply to Taketo Sato

TI__Genius 10975 points

Hello Taketo,

That is a good point that I did not consider. I'll double check with my team tomorrow once they're back in office and get back to you.

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

Thanks for double checking with your team. I wait for feedback from the team.

Best regards,

+1 Andrea Vallenilla 10 months ago in reply to Taketo Sato

TI__Genius 10975 points

Hello Taketo,

Sorry for causing any confusion. You are correct, Vdd voltage needs to be powered before Vddo (corrected after posting since customer caught mistake), if not you'll damage the ESD internal circuitry. Let me know if there's still something unclear.

Best,

Andrea

0 Taketo Sato 10 months ago in reply to Andrea Vallenilla

TI__Genius 9975 points

Hello Andrea-san,

I understand the recommended sequence, Vdd first then Vddo.

(Maybe you have typo in previous response but I understand it.)

Best regards,

Clock & timing

Clock & timing forum

LMK00105: Fixed output, Power sequency requirement