CDCE6214-Q1: CDCE6214-Q1 shcematic review

peter zhou

Prodigy 10 points

Part Number: CDCE6214-Q1

help to review schematic，how to terminaed about LPHCSL output(Add seried resistors,ac caps?)，thanks.

8 months ago

0 Kadeem Samuel 8 months ago

TI__Genius 15040 points

Peter,

Typically 0-Ohm resistors are placed in series with the output clocks to allow for swapping out with a different value for better impedance matching or amplitude attenuation.

Ensure that REFSEL is pulled low to select SECREF as the input clock.
We recommend using an additional ferrite bead + capacitor for isolating VDD_VCO from the other VDD domains.

Thanks,

Kadeem

0 peter zhou 8 months ago in reply to Kadeem Samuel

Prodigy 10 points

thanks ，

1.when use SECREF as clock，how to deal with PRIREF pin 5 and pin 6？

2.For clock output connecto to SSD（MTFDHBL128TDQ-1AT12ATYY） PCIE ref clock，do we need to add 100ohm at SSD side？

0 Kadeem Samuel 8 months ago in reply to peter zhou

TI__Genius 15040 points

Peter,

The PRIREF pins can be left disconnected when only SECREF is used.

The outputs of the CDCE6214-Q1 are LP-HCSL rather than HCSL, so 50Ohm termination resistors to GND are not needed.

Thanks,
Kadeem

Clock & timing

Clock & timing forum

CDCE6214-Q1: CDCE6214-Q1 shcematic review