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LMK04828: Two questions about LMK04828B

shen jie
Prodigy 245 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMX2594, TIDA-01021

Hi, all:

I have two questions about LMK04828B：

1.  Could cascaded zero-delay or nested zero-delay all be used to realize a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs? 

2. In the application note about TIDA-01021(Multichannel JESD204B 15-GHz Clocking Reference Design), it is mentioned that SDCLKout of  LMK04828B should output logic high to let LMX2594 work in master mode.

Firstly, SDCLKout pin is made conditionally low. But then, how to exchange the positive and negative signals of differential pair? I couldn't find any register about changing polarity of differential pin?

Thanks in advance!

Best regards!

Jason

  • 0
    TI__Expert 8401 points

    Jason,

    1. Yes, but there is a difference in how this is achieved.   Cascaded 0-delay mode will create a fixed phase relationship from the input of PLL2 (OSCin) to the outputs.  In dual loop mode the input to PLL1 (CLKinX) will have a fixed phase relationship to the output of PLL1, which happens to be the input the PLL2 (OSCin).  Therefore because CLKinX is related to OSCin and, in cascased 0-delay mode, OSCin is related to the outputs, CLKinX is related to the outputs.  Nested 0-delay mode, on the other hand,  will create a fixed phase relationship directly from the input of PLL1 (CLKinX) to the outputs (as shown in the diagram you sent).

     2. I believe that this in reference to the physical wires from the output to the balun being exchanged so that the signal's polarity is flipped. 

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi, Will:

    Thanks for your response in time!

    1. 1. Yes, but there is a difference in how this is achieved.   Cascaded 0-delay mode will create a fixed phase relationship from the input of PLL2 (OSCin) to the outputs.  In dual loop mode the input to PLL1 (CLKinX) will have a fixed phase relationship to the output of PLL1, which happens to be the input the PLL2 (OSCin).  Therefore because CLKinX is related to OSCin and, in cascased 0-delay mode, OSCin is related to the outputs, CLKinX is related to the outputs.  Nested 0-delay mode, on the other hand,  will create a fixed phase relationship directly from the input of PLL1 (CLKinX) to the outputs (as shown in the diagram you sent).

    [Jason]: As above words marked red, because there is no clock divider after external VCXO at output of PLL1, it create a fixed phase relationship between the input to PLL1(CLKinX) and output of PLL1, right? 

    2. I believe that this in reference to the physical wires from the output to the balun being exchanged so that the signal's polarity is flipped.

    [Jason]: Yes, you are right. I check the schematic, and N is connected to + , P is connected to -. This detail is not easy to be discovered if no enough carefulness.

    Thanks again!

    Best regards!

    Jason

  • +1 in reply to shen jie
    TI__Expert 8401 points

    Jason,

    1. Exactly, you are correct.

    Let me know if you have any further questions.

    Regards,

    Will