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LMK04828: Question about how to realize deterministic phase relationship between output clocks from LMK04828B on the different board

shen jie
Prodigy 245 points
Part Number: LMK04828
Other Parts Discussed in Thread: TIDA-01021

Hi, 

My test setup as below figure shown, signal generator(E8257D) provide reference 10MHz clock to CLKin0 pin of respective LMK04828B on the different board through PD1, for common clock reference;

Another demo board provide the one-shot SYNC pulse to SYNC pin of respective LMK04828B on the different board through PD2, for reset the internal divider .

After one-shot SYNC, I can see that alignment between 5M sysref on the respective LMK04828B. But there is some residual skew between them, about 315ps as below figure shown. Through many power on/off, this kind of residual skew would exist and change, such as -36ps or 61ps. It seems that  phase relationship is not fully deterministic. Maybe my way is wrong. So, How could I do to realize deterministic and alignment phase relationship between output clock from LMK04828B on the different board?

Thanks in advance!

Best regards!

Jason

  • 0
    Prodigy 245 points

    Hi，

    Attach the .tcs file

    250M_PL_125M_SYSREF_5M.tcs

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Expert 8401 points

    Shen,

    I will get back to you by Monday.  

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi, William:

    Add some other test results: 125M clock output from DCLKout of LMK04828B.

    The below are clock waveforms of two LMK04828B on the different board for three times power on/off. This kind of residual skew change very obviously。

    Up till now, is there any mistake operation in the my process of synchronization across multi-LMK04828B across boards?

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Expert 8401 points

    Jason,

    You can find an app note about the various approaches to synchronizing multiple LMK04028s here.  This e2e thread also I believe should answer your question here.  

    Please let me know if it does not help, and you need support!

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi，William：

    Many thanks for your response! Later on I will read the app note and e2e thread mentioned by you.

    But now, could you please help me check the above post and give me some suggestion firstly? About synchronizing multiple LMK04028s, I have done the common clock source and the alignment single SYNC pulse sent to the LMK04828s on the different board. I don't use zero-delay mode for LMK04828. Only divider reset simultaneously is enough for aligning clock output on the two LMK04828B? Do you see this kind of residual and non-deterministic skew during multi-LMK04828B synchronization before?

    Sorry for my many questions to you. Thanks again!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Expert 8401 points

    Shen,

    Sorry for the delay, I will get back to you tomorrow.

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    TI__Expert 8401 points

    Shen,

    shen jie said:
    Only divider reset simultaneously is enough for aligning clock output on the two LMK04828B?

    No.  Your current configuration will not be able to achieve deterministic synchronization.  This is because the sync pulse will synchronize the SYSREF divider to the VCO output which is not deterministic to the VCO on the other LMK04828 therefore resulting in the skew.

    In order to create a deterministic relationship you will need to use nested 0-delay mode to create a phase relationship between your input and SYSREF signal.  Then, when you reset the dividers with a SYNC you should see your SYSREF signal without any skew.  I have attached an updated config file with the necessary changes.  

    You may also need to adjust the loop filter components to achieve lock.  

    Regards,

    Will


    250M_PL_125M_SYSREF_5M_nested_0_delay.tcs

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi，William:

    According to your suggestion, I make below .tcs file which enable Zero-delay SYSREF mode and SYNC too.

    250M_PL_125M_SYSREF_5M_ZDM with SYNC.tcs

    the process is listed below:

    1. use this .tcs to program the respective LMK04828B on the different board.

    2. make SYSREF_CLR=1

    3. use external SYNC signal sent to the SYNC pin of the two LMK04828B respectily, t

    4. make SYNC_DISx =1 and SYNC_DISSYSREF =1

    5. make SYSREF_CLR=0，then SYSREF_MUX=3(Continuous mode)

    many times of power on/ off, 5M sysref clocks just are full 180deg out of phase always

    and 125M clock are 180deg out of phase too

    At this moment, I remember that input10M reference clock is great than output 5M sysref  clock which loopback to N divider of PLL1. Is it violate the first rule of ZDM mentioned in the application note of "Multi-Clock Synchronization"?  Every power on/off phase difference always is 180deg. It seems that phase relationship is deterministic but not alignment.

    So, I try to change the 10M reference clock to 5M reference. Test show that 5M sysref clock just always are in the phase.

    Many thanks to you !

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Expert 8401 points

    Jason,

    You are correct, the 10 MHz would not always align with the correct edge.  I am glad you have it working now. 

    Regards,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi，William:

    OK, I see. There is a last question which puzzle me：

    I found that this kind of  SYSREF zero-delay mode which input reference clock is great than output SYSREF clock appear in the many application note, such as " TI Designs: TIDA-01021,  Multichannel JESD204B 15-GHz Clocking Reference Design for DSO, Radar, and 5G Wireless Testers". In this note, test case2 for Multichannel Clock Skew Measurement make LMK04828B work at single PLL2 mode with input 100MHz reference clock , and  loopback 25MHz SYSREF to N divider of PLL2 for zero-delay mode. This situation also violate first rule of ZDM which require the GCD Between Input and Output Frequency must Equal Input Frequency, so frequency plan could not result in deterministic clock phase, right？ Since it is so, why test case2 in the application note use  this ZDM?  Also I think it is the similar situation with .tcs given by you in the above post (10MHz input reference clock and 5MHz output sysref clock which loopback to N divider of PLL1 for zero-delay mode)

    Thanks in advance!

     

    Best regards!

    Jason

  • +1 in reply to shen jie
    TI__Expert 8401 points

    Jason,

    shen jie said:
    first rule of ZDM which require the GCD Between Input and Output Frequency must Equal Input Frequency

    This rule is applicable only to automatically create determinism in ZDM without a SYNC necessary.  But because we have a SYNC pulse to synchronize everything, we can violate this rule.  Your configuration is no longer intrinsically deterministic, but deterministic after a SYNC event.  

    I hope this helps,

    Will

  • 0 in reply to William Pfennigwerth
    Prodigy 245 points

    Hi, William:

    I read below thread accidently. In this thread, it is the same situation that 10MHz input reference clock and 2MHz sysref clock which loopback to N divider of PLL1 for zero-delay mode. Ajeet Pal suggest that it is no necessary to reset sysref divider cause ZDM have ensured the edge of output sysref on the different board are aligned if every LMK device sees the reference clock at the same phase. But you said that this kind of ZDM is no longer intrinsically deterministic without SYNC. So, I'm  puzzled again:(

    e2e.ti.com/.../lmk04828bevm-multi-chip-configuration-initially-in-phase-right-after-sync-pulse-then-come-out-of-phase

    Thanks in advance!

    Best regards!

    Jason

  • +1 in reply to shen jie
    TI__Expert 8401 points

    Jason,

    Ajeet is incorrect in this answer.  If you continue reading the thread you can see that the customer was unable to have a synchronized sysref without the sync event.  

    Regards,

    Will