This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK03328: Jitter cleaning mode

Part Number: LMK03328
Other Parts Discussed in Thread: , LMK04832


In my application, I have a clock of around 70MHz. This clock has significant jitter. I need to double this clock and filter the jitter as much as possible.

I am struggling, however, to configure the LMK03328 to optimally clean jitter clean.

I am prototyping on the development kit LMK03328EVM.

With TI PLLatinum Sim, i have tried to set the loop bandwidth to the minimum - the LMK03328 advertises down to to 200Hz in its datasheet - but I do not manage to get this below 1kHz.

I have set Kpd to its minimum value of 0.4mA,

I have set PLL1_CLSD WAIT[1:0] to 0x3

I have set PLL1_LOOP BW to 1

Are there any additional points of attention? Does TI PLLatinum take "PLL1_LOOP BW = 1" into account?

Thank you for your support!

  • Sciocp,

    PLLatinum Sim does not factor in the PLL1_LOOPBW bit.
    The TICS Pro software has this description for the bit: "When PLL1_LOOPBW is 1 the loop bandwidth of  PLL1 is reduced to 200Hz. When PLL1_LOOPBW is 0 the loop bandwidth of PLL1 is set to its normal range."

    The input divider on the reference path will also impact the loop bandwidth.

    For a reference clock that is very high jitter, a cascaded-pll device such as the LMK04832 may be optimal over the LMK03328: