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CDCE6214-Q1: LVCMOS polarity and synchronization. Replace CDCI6214.

wang shu
Prodigy 240 points
Part Number: CDCE6214-Q1
Other Parts Discussed in Thread: CDCI6214, CDCE6214, LMK05318B

Hi,

I wish to replace the CDCI6214 to CDCE6214.

In TICS Pro. The CDCI6214 can set the LVCMOS output to CMOSP, CMOSN, and CMOSPN. Then it alos can set to P+ N+, P+ N-, P- N+, P- N-. what does these mean? I think the P+ N+ are the polarities. so i don't understand the CMOSP, CMON, and CMOPN configuration.

About the CDCE6214, the software can only set output to CMOSP, CMOSN, CMOSPN. How to set the polarity? the datasheet show register R59[12], R75[12] and R59[11], R75[11] control the polarity. how to do it in the software? If the CMOSP/N is the polarity, so what is the P+ N+ in CDCI6214 configuration?

CDCI6214 configuration:

CDCE6214 configuration:

One more question: Both CDCI6214 and CDCE6214 has external synchronization function. It can use ch{x}_sync_delay to achieve a fixed delay up to 32 cycles.

1. what is the cycle frequency? the VCO frequency?

2. if i make the sync dealy to 10 cycles. Is that mean the delay between SYNC pin rising edge to outputs first edge is 10 cycles?

3. how to set it in CDCE6214 configuration page. i can find sync function and delay in CDCI6214 configuration page. not in CDCE6214.

Best Regards,

Shu

  • 0
    TI__Genius 15080 points

    Wang,

    You are correct that these are the polarities. In the User Controls page, the polarity can be set for the CDCE6214 as well:

    The chx_cmosp_pol and chx_cmosn_pol fields set the polarity. 

    For the synchronization delay, each "cycle" is a period of the VCO clock. If the delay is 10 cycles, then the output clock will be delayed by 10 VCO cycles relative to the other output clocks. The sync delay field is also present in the User Controls page above - the SYNC needs to be enabled (chx_sync_en), and then the sync delay set.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 240 points

    Thanks Kadeem,

    So if i wish the CDCE6214 outpu1 p and n generate same phase LVCMOS clocks,  i should disable the "ch1_cmosp_pol" and enable the "ch1_cmosn_pol". am i right?

    what the different between the CMOSP/N and P+/N+ in CDCI6214 configuration? if I chose CDCI6214 output 2 to CMOSPN and P+/N+. what type clocks they are? i wish to verify i didn't make wrong on my existing CDCI6214 application.

    For the synchronization delay, so it is the time between the outputs. not between the SYNC signal and outputs.

    I wish to know the time between SYNC rising edge on PDN pin and outputs in below figure. Is it a fixed value or an evaluated value? if it is not for different devices, is it a fixed time for each CDCI6214 after it is power on.

    How do i know or set the time between SYNC rising edge and outputs?

    actually, i wish to align these outputs and one internal clock in my controller. i am going to use a SYNC signal to synchronize the outputs, but i cannot evaluate the phase between the outputs and the internal clock. Now it is a random time in my CDCI6214 application.

    Best Regards,

    Shu

  • +1 in reply to wang shu
    TI__Genius 15080 points

    Shu,

    The default output of the P and N clocks is in phase. Setting the polarity bit to a '1' will add a 180 degree phase shift. The clocks will be the same phase if the polarity bits are the same value. ch1_cmosn_pol and ch1_cmosp_pol both being '0' is equivalent to P+/N+.

    The PDN pin behavior needs to be changed from reset to sync for using the SYNC feature through GPIO control. Otherwise, a bit can be written via I2C.

    The timing is detailed below:

    The timing is 4 clock cycles of the respective output from tristate to the first valid rising edge. This time is not necessarily the same each time.

    Note that for deterministic behavior from the input to the output, the reference divider/doubler cannot be used (/1).

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 240 points

    Kadeem,

    Thanks!

    Is there any way to synchronize my controller clocks and these CDCE6214 outputs if the time is not same each time. I can upgrade my hardware design if it is necessary.

    Best Regards,

    Shu

  • 0 in reply to wang shu
    TI__Genius 15080 points

    Shu,

    Is the controller clock the input clock in this case? If so, zero-delay mode would be needed for synchronizing the outputs to the input. In order for this to work, one of the non-OUT0 outputs needs to be routed to the SECREF input with the same frequency as the PRIREF source. As all of your outputs are in use with the configuration provided above, this feature cannot be used here. The LMK05318B offers the zero-delay functionality with the required number of outputs.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 240 points

    Kadeem,

    Thanks. I may find another way to synchronize the controller and output. 

    I get a new question when design the CDCE6214 hardware. The input need 100ohm termination and ac-coupling. The CDCE6214 input clock is from a clock buffer with ac-coupling output in my design. So does it need the ac-coupling again before the CDCE6214 inputs?

    I checked the CDCE6214EVM. It does two ac-coupling and a 100ohm termination before the clock inputs. Do i need to follow the same design? one ac-coupling is close to the source, one ac-coupling is close to CDCE6214 inputs.

    Best Regards,

    Shu

  • 0 in reply to wang shu
    TI__Genius 15080 points

    Shu,

    Only the AC coupling close to the CDCE6214 is required.

    Thanks,
    Kadeem