This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK6C: PCB Layout Review for LMK6C012288

Part Number: LMK6C
Other Parts Discussed in Thread: TLV1117LV

Hello E2E Team,

Kindly guide below LMK6C - 12.288MHz BAW Oscillator layout is acceptable.

  1. U4: LMK6C012288
  2. C8 & C9: 0.1uF 0603 MLCC
  3. Pin 3: Oscillator out - 12.288MHz
  4. Pin 1: OE Pin interfaced with MCU
  5. 2-Layer PCB with 60um Copper thickness & 1.5mm FR4

Kindly also comment if below is acceptable:

  1. Ground Pin of the LMK6C is shared with MCU's decoupling capacitor for a compact layout both connected to solid ground on bottom layer.
  2. Oscillator Trace is ~6mm in length with 0.275mm width with solid ground on the bottom layer
  3. instead of 1uF MLCC we have used 2x 0.1uF MLCCs in 0603 package
  4. The Power supply has a -30dB upto ~1GHz ferrite bead Pi Filter at the input
  5. TLV1117LV for 5V to 3.3V is used post Pi-Filter

Do we need to be concerned about reflections/decoupling MLCC values/layout?

  • Hi Neet, 

    Thanks for sending over the layout, here is my feedback:

    1. Yes, sharing a large ground plane is usually preferred so I don't see any concerns with this 

    2. Is the trace impedance matched to 50 Ohms? I ran the numbers you provided through a calculator and I'm seeing the trace impedance is around 120 Ohms (see image below). If I entered the information correctly, then it be worth considering a change to the board stack-up (maybe switching to 4 layers if possible) so that there is less height between the top layer and a ground plane. This should make it easier to create a trace with 50 Ohm impedance that still has a reasonable width.

    However, since the overall trace length is so small the transmission line effects might not make much of a difference in terms of reflections or signal integrity. Altium should have a built-in signal integrity analysis tool you can use along with the LMK6C IBIS model which I've attached here. If the signal integrity simulation shows there are any issues then I would recommend switching to a 50 Ohm trace impedance. 

    3. Using 2x0.1uF decoupling capacitors should also be fine

    4. There could be some impact on the output phase noise performance due to power supply noise. However, with the decoupling capacitors and the LMK6C's internal LDO, I think most of the power supply noise should be rejected. 

    5. See point above 

    Let me know if you have any other questions. 




  • Hello ,

    Thank you for your review & your comments. We have further tried to make the layout more compact with a goal to reduce the trace length further & minimize the chances of crosstalk between Clock trace & Enable trace.

    1. Kindy suggest if it is okay to add a Ground Via (0.6mm Diameter with 0.3mm Hole) below the LMK6C IC?
    2. Also let me know if 2 Vias to Ground plane are sufficient for this device as the ground plane surface available is limited in this layout configuration.
  • Hi Neet, 

    With this more compact layout I'd expect better signal integrity on the output since the trace length is shorter. Just out of curiosity, when you mentioned crosstalk between the clock and the enable trace, do you plan to rapidly toggle the oscillator on/off during operation? I wouldn't expect crosstalk from the OE to have an impact on the clock output for most applications. 

    For your other questions, yes it should be fine to add a via underneath the LMK6C as long as it passes all design rule checks in terms of distance/spacing. 2 Vias to the ground plane should be sufficient since the return current should be relatively low in this circuit. 



  • Hello Cannor,

    Thanks for your feedback. Key reason for my concern over cross-talk was from hypothesis that the rise times for the LMK6C device is 0.5ns & this might induce some form of coupling with the enable trace - we are using this oscillator source for the first time & hence we would kindly appreciate from your practical based experience if we are to be concerned about coupling into the enable signal trace given close proximity to the clock signal trace which is not impedance matched but us small in length ~1cm 

  • Hi Neet, 

    Got it, yes there could be some amount of crosstalk from the clock output to the OE pin, but I would expect this to be on the order of uV or maybe a few mV at the most. Since the OE pin is just a simple logic signal and has a pretty wide margin for the on/off thresholds ( OE < 0.6V is considered "low", OE > 1.3V is "high") I wouldn't expect this to be an issue. Let me know if you have any other questions.