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LMK03328: Startup time in jitter cleaning mode

Part Number: LMK03328

Hello,

In my application, I have a clock with significant jitter. I need to double this clock and filter the jitter. I am currently prototyping on the LMK03328EVM development kit.

With my current settings, the LMK03328 provides a proper jitter clean clock output.

However, I am struggling to have a startup time as indicated by the datasheet §12.2.

PLLx_LOOP BW is set to 1, PLL CL wait is set to 300 ms and PLL1 VCO wait is set to 0.4 ms. R12.1 is set to 1 (parallel calibration of both PLLs). No crystal is used.

From equation 5 or 7 I'd expect the PLL startup time to be 0 (TXO) + 300 ms (TCal) + 0.4 ms (TVco) + 20 ms (Tlock ~ 4/LBW; LBW = 200 Hz), in total 320.4 ms.
However, when measuring from a soft reset till PLL LOL de-asserted, I measure at least 1.8 seconds. This is when a VCO around 4900 MHz is selected, for higher VCO it takes even longer.
Input clock is already available and stable at the time of soft reset.

Are there any points of attention to reduce this startup time? I have already provided the TICS Pro .tcs file in attachment.

Thank you for your support!

LMK03328_20240429.tcs

  • Jdery,

    The PLLx_LOOP_BW bit adds a delay time before starting the VCO calibration. With this bit set to a '0', do you see the startup time reduced?
    Thanks,
    Kadeem

  • Hi Kadeem,

    This reduces the startup time by only a 67 ms. Which means there is still a gap of around 1.4 seconds. 

    Thank you,
    Jdery

  • Jdery,

    I am checking this on the Bench this week, and will let you know my result by tomorrow.

    Thanks,

    Jadeem

  • Jdery,

    What version of the TICS Pro software are you using? When I try to load your configuration, I encounter errors.

    With a normal configuration, I see a startup time of ~8ms. If you can let me know what your Inputs/PLLs, Outputs, and Status pages look like, I can create and test a configuration for you.

    Thanks,
    Kadeem

  • Hi Kadeem,

    I am using TICS Pro version 1.7.7.2.

    Attached you can find screenshots of the requested pages. Maybe also worth adding is that the PLL charge pump gain is set to 0.4 mA.

    Thanks,
    Jdery

  • Jdery,

    Please use the maximum charge pump gain. With maximum gain, do you still see a long startup time?
    I will review the configuration, but I will not be able to check this on the bench until Monday due to travel.
    Thanks,
    Kadeem

  • Hi Kadeem,

    Using maximum charge pump gain has no effect on the long startup time.
    Looking forward to your findings next week.

    Thanks,
    jdery

  • Jdery,


    Finally got it working with your setup. I do in fact see a very long startup time, as you indicated:

    The new configuration that I have created (from taking an existing configuration and setting the necessary fields to your values) takes the startup time down to ~4ms, and powers off unused outputs for lower current consumption:

    LMK03328_Updated_Configuration.tcs

    Thanks,
    Kadeem

  • Hi Kadeem,

    With your configuration, I also have a startup time around 4 ms.
    However, to meet our jitter requirement on the clock output I had to adjust the charge pump gain to 0.8 mA (with 0.4 mA, the PLL doesn't lock anymore). Setting PLLx_LOOPBW back to '1' extends the startup time a bit, but there the charge pump gain also needs to be 0.8 mA to sufficiently clean up the jitter. Is this expected behavior? I was expecting that the charge pump gain would have no influence once in jitter clean mode.

    After comparing my configuration with your configuration, it looks that the PLLx_CLSDWAIT is causing the long startup time. When I set it from 0.3 ms to 30 ms, the startup time extends with around 160 ms. Setting it to 300 ms brings the startup time back to the 1.8s observed earlier. 
    Table 21 in the datasheet mentions 'programmable cycles of internal oscillator', while the selectable values in TICS Pro are expressed in time (0.3 ms, 30 ms, ...). Is there any other setting or pin strapping on the EVM board that could influence this? 

    Thank you for the clarifications,
    jdery

  • Jdery,

    Larger charge pump current will yield better performance - please go ahead and increase the charge pump current.

    This setting essentially sets the length of a wait timer while the PLL is achieving lock. My understanding is that the timing listed is moreso a minimum timing rather than a strict time, with the actual lock time depending on the number of attempts for the PLL to lock. There are not EVM settings that affect this. I have reached out to the designer for more insight on the exact changes in the internal state machine when this field is changed, and will let you know what I hear from them.
    Thanks,

    Kadeem

  • Jdery,

    The PLLx_CLSDWAIT fields control the delay between when the VCO capacitor code is changed and when the VCO tuning voltage is compared against the comparator thresholds. As there is delay between the capacitor code changes, this will result in a greatly increased startup time.

    Thanks,
    Kadeem