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CDCE6214: LP-HCSL default output setting

Part Number: CDCE6214


Hi team,

  1. My customer would like to use LP-HCSL 100MHz output without programming.
    Just to make sure, to obtain 100MHz LP-HCSL, HW_SW_CTRL pin must be Low which loads page 0.
    Is this understanding correct?
    The datasheet page 40 states opposite setting as below.
    The device is factory-configured to provide:
    • 100-MHz LVDS with 25-MHz XTAL when HW_SW_CTRL=L. The 25-MHz output on OUT0 is enabled.
    • 100-MHz LP-HCSL with 25-MHz XTAL and HW_SW_CTRL = H. The 25-MHz output on OUT0 is enabled.
  2. When using page 0(HW_SW_CTRL=L), default setting of PDN/SYNCN pin is PDN?
    The customer would like to disable output to save power during the device is not used.
  3. They would like to prevent rewriting of setting via I2C.
    At page 33 of the datasheet, it states "For factory programmed device, I2C interface is not available when HW_SW_CTRL is LOW.".
    Is HW_SW_CTRL pin dual function(control access of I2C and EEPROM page select)?

Best regards,

Shota Mago

  • Shota,

    We will verify and get back to you early next week as Monday is a US holiday.



  • Shota,

    1. Yes, when the HW_SW_CTRL = L, page 0 is loaded. There is a mistake in the datasheet, when HW_SW_CTRL = L the 100 MHz LP_HCSL output is enabled on OUT1-OUT4.

    2. Yes, you are correct. The PDN_INPUT_SEL field has a register bit address of R0[14]which is set to 0 when HW_SW_CTRL = L.

    Also kindly note the following about the configuration of the PDN pin as well as other information in the datasheet: "For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin until VDD pins have reached 95% of its final value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI recommends to add a capacitor to GND on PDN pin to delay the release of reset."(Page 5)

    3. Correct, setting HW_SW_CTRL = L will both select page 0 of the EEPROM and also disable the I2C interface.