LMK04832-SP: LMK04832-SP

All delays (Local and Global SYSREF delay, as well as device clock delay) are denominated in clock distribution path cycles. For example, with a VCO frequency of 3054MHz, one cycle of any of SCLKx_y_DDLY, SYSREF_DDLY, or DCLKx_y_DDLY would shift the edge by 1/3054MHz = 0.33ns. Device clock half-steps use the falling edge of the clock distribution path, which for VCO is almost exactly 50% duty cycle; for external clocks with non-50% duty cycle (Fin0 or Fin1) this may not be the case. SYSREF half-steps are unfortunately weirdly implemented – there can be several tens of picoseconds of error in the timing of the half-step. I’m not sure why. So SYSREF half-step is only an approximate half-period of the clock distribution path; it does nominally scale with the clock distribution period, just with a constant offset that becomes noticeable for shorter clock distribution path periods.

The diagram in TICS Pro is deficient in conveying how this function works. I will correct the positioning and source of the delay counter on the outputs page and on the SYNC/SYSREF page for the next release, placing the DCLKx_y_DDLY counter and the SYSREF_DDLY counters before their respective dividers, and making it obvious that the SCLKx_y_DDLY is also denominated in clock distribution path cycles. There’s a few other things I’ve noticed that should also be updated (SYNC_DISSYSREF on clock outputs page should be stylized with a similar AND gate, and should probably show the SYSREF_MUX for clarifying the origin of the SYNC/SYSREF distribution mechanism; DDLY_PD functions should probably be modified in default configurations to “off” since they are only required for dynamic digital delay, and the dimming logic for when this occurs should be handled differently).