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Original question:

LMK1C1102: Operating from VDD=+3.0V

LMK1C1102: LVCMOS clock voltage down translation 2.5V into 1.8V

Mario Simunic
Prodigy 10 points
Part Number: LMK1C1102

Tool/software:

Hi,

I've read in product selection matrix a Function Column of LMK1C1102 as "Clock buffer, Level translator, Single-ended".

I'm looking for solution to voltage level translate a clock from MEMS oscillator output LVCMOS 2.5V into FPGA input LVCMOS 1.8V.
Idea is to Supply LMK1C1102 with 1.8V, where CLKIN would be driven by LVCMOS 2.5V clock signal.

There is no clear documentation of input protection of LMK1C11xx series. It can only be assumed that protection won't be triggered until (Vdd + diode) voltage and it's ok while under absolute maximum rating of 3.6V.
Translating 1.8V into 2.5V is not possible due to V_IH = 0.7*2.5 =  1.75 it presents too narrow margin from 1.8V.

Please could you clarify input protection and how to use this device as Level translator and clock buffer?

Thanks.

  • +1
    TI__Expert 8231 points

    Mario,

    Yes, the LMK1C1102 will work for your configuration.

    The LMK1C clock inputs are fail safe as described here.

    There is no input protection for VDD or the clock input past the Absolute Maximum Ratings, which when exceeded or undershot can cause permanent device damage.  As long as you stay within these specs the part will function.  

    Finally, yes you are correct, translating  from 1.8V to 2.5V is not possible due to V_IH = 0.7*2.5 = 1.75 which is < 1.8V.

    Regards,

    Will