Tool/software:
Hi all, Hi Dean Banerjee,
I have a design done with the device LMK04806B with PLLatinum Sim.
I have calculated the PLL phase noise according to the given FOM and PN10kHz metrics. The result looks very reasonable to me.
At 100 Hz frequency offset I get -96 dBc/Hz and the floor is at -109 dBc/Hz.
But the result is different to the shown PLL phase noise PSD in PLLatinum for higher frequency offsets,
which shows that the closed loop filter for the PLL seems to be included (what I agree to).
What I do not understand is the low frequency case:
The closed loop transfer function of the PLL should be around + 47 dB at 100 Hz, i.e. the PLL PSD should be increase at 100 Hz by this value and give -97 dBc/Hz + 47dB = -50 dBc/Hz
But it seems the increase is none (0 dB). The overall PLL phase noise is still around -94 dBc/Hz at 100 Hz frequency offset:
So I am missing something here, but what ??
Thanks a lot
Regards,
Markus