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CDCEL937-Q1: CDCEL937-Q1 I2C communication error

Part Number: CDCEL937-Q1

Tool/software:

Hi, We am using CDCEL937-Q1 clock buffer for our project.

According to the datasheet S1 and S2 pins will act as I2C SDA and SCL as default.

We am trying to read/write registers of clock buffer, according to the data sheet if byte read/write to be done then MSB should be 1. If we need to read/write register 0x34 then command code we need to send is 0xB4. Let me know whether our understanding is correct.

I am using below api to read/write the clock buffer register. The function return success after I2C write but If we read the register again the value is got is 0. Check whether below API is correct to read/write the clock buffer register.

API:

uint8_t clock_buffer_i2c_rw(uint16_t slave_addr, uint8_t reg,

uint32_t *argval, uint8_t len,

uint8_t mode, uint16_t timeout)

{

HAL_StatusTypeDef err = HAL_OK;

uint32_t i2c_errcode = 0;

uint8_t regdata[10];

uint32_t value = 0;

if(mode > I2C_MODE_READ || len > 4 || !argval)

{

return ERRCODE_INVAL;

}

hi2c2.ErrorCode = HAL_I2C_ERROR_NONE;

switch (mode) {

case I2C_MODE_READ:

regdata[0] = reg;

err = HAL_I2C_Master_Transmit(&hi2c2, slave_addr ,

regdata, 1, timeout);

if(err != HAL_OK) {

i2c_errcode = HAL_I2C_GetError(&hi2c2);

printf("\n\r %s READ MAster Transmit Error !! "

" - 0x%02x 0x%08lx REG = 0x%04x for slave 0x%02x \n\r",__func__,

err, i2c_errcode, reg, slave_addr);

__HAL_I2C_DISABLE(&hi2c2);

/* Delay for I2C peripheral settling */

HAL_Delay(1);

__HAL_I2C_ENABLE(&hi2c2);

if(i2c_errcode == HAL_I2C_ERROR_TIMEOUT ||

i2c_errcode == HAL_I2C_ERROR_AF ||

err == HAL_TIMEOUT)

{

return ERRCODE_AGAIN;

}

return ERRCODE_IO;

}

else

{

printf("1HAL_I2C_Master_Transmit Pass \n master_status_flag:%d \n\r", master_status_flag);

}

memset(regdata, 0x0, sizeof(regdata));

err = HAL_I2C_Master_Receive(&hi2c2, slave_addr ,

(uint8_t *)regdata, len , timeout);

if(err != HAL_OK) {

i2c_errcode = HAL_I2C_GetError(&hi2c2);

printf("\n\r MAster Receive Error !! - 0x%02x 0x%08x for slave 0x%02x "

" for REG - 0x%04x \n\r", err, i2c_errcode, slave_addr, reg);

if(i2c_errcode == HAL_I2C_ERROR_TIMEOUT ||

i2c_errcode == HAL_I2C_ERROR_AF ||

err == HAL_TIMEOUT)

{

return ERRCODE_AGAIN;

}

return ERRCODE_IO;

}

switch (len) {

case 1:

*(uint8_t *)argval = regdata[0];

break;

case 2:

*(uint16_t *)argval = regdata[0] << 8 | regdata[1];

break;

case 4:

*argval = regdata[0] << 24 |

regdata[1] << 16 |

regdata[2] << 8 | regdata[3];

break;

}

//printf("value %ld \n\r", *argval);

break;

case I2C_MODE_WRITE:

value = *argval;

regdata[0] = reg;

printf("value %d*********\n",value);

switch (len)

{

case 1:

regdata[2] = (value & 0x0000FF);

break;

case 2:

regdata[2] = (value & 0x00FF00) >> 8;;

regdata[3] = (value & 0x0000FF);

break;

case 4:

regdata[2] = value >> 24;

regdata[3] = (value & 0xFF0000) >> 16;

regdata[4] = (value & 0x00FF00) >> 8;

regdata[5] = (value & 0x0000FF);

break;

}

err = HAL_I2C_Master_Transmit(&hi2c2, slave_addr ,

regdata, 1+len, timeout);

if(err != HAL_OK) {

i2c_errcode = HAL_I2C_GetError(&hi2c2);

printf("\n\r WRITE MAster Transmit Error !! "

" - 0x%02x 0x%08lx REG = 0x%04x for slave 0x%02x \n\r",

err, i2c_errcode, reg, slave_addr);

__HAL_I2C_DISABLE(&hi2c2);

/* Delay for I2C Peripheral settling */

HAL_Delay(1);

__HAL_I2C_ENABLE(&hi2c2);

if(i2c_errcode == HAL_I2C_ERROR_TIMEOUT ||

err == HAL_TIMEOUT)

{

return ERRCODE_AGAIN;

}

return ERRCODE_IO;

}

break;

}

return ERRCODE_SUCCESS;

}

Function call to read:

clock_buffer_i2c_rw(0xDB,0xB4, &dataVal, 1,I2C_MODE_READ, LONG_TIMEOUT );

Function call to write:

dataVal = 0xE5;

clock_buffer_i2c_rw(0xDA,0xB4, &dataVal, 1,I2C_MODE_WRITE, LONG_TIMEOUT );

This API is standard API which we have used for other peripherals also, it is working fine as expected. Let me know whether anything need to be handled for clock buffer read/write.

  • Kaviya,

    If you are performing a write, then the structure should be start, write the target address (with write bit), write 0x34, then write data. For a read, this should be write target address (with write bit), write 0xB4, repeated start + target address (with read bit), read back the data byte, then stop. This is shown below:

    Can you add print statements in your code to confirm that the sequence above is being followed, especially with regard to the read structure?

    Thanks,

    Kadeem