Tool/software:
Hello
OSCin=10.23, RFout=10.23*8
This belongs to Category 2.
Do I have to use a SYNC pin for this case?
Do I need to follow 7.3.12.3 Procedure for Using SYNC?
Original question:
Tool/software:
Hello
OSCin=10.23, RFout=10.23*8
This belongs to Category 2.
Do I have to use a SYNC pin for this case?
Do I need to follow 7.3.12.3 Procedure for Using SYNC?
Hello Jae,
If operating in CAT2 Sync you can toggle VCO_PHASE_SYNC bit.
Regards,
Vicente
Hi Jaeheung,
I cannot follow what you're trying to explain can you please elaborate?
As mentioned, you can use PSYNC pin and send a rising edge to phase synchronize the device or you can also toggle the VCO_PHASE_SYNC bit from 0 to 1 to enable phase sync. Please note the software toggle only works for a CAT2 sync.
That is correct,
If the VCO has not locked, the outputs will be muted. 
Regards,
Vicente
Hello
1)
I attached the SPI Register table file, TICS Pro load file, and PLLatinum Sim load file.
Could you check these files?
Could you present the example to get an output frequency?
2)
Can the unoptimized loop filter coefficients cause the output to be muted?
3)
PLLatinum Sim presents the Design Warning for the loop filter.
Could you recommend the coefficients for the loop filter?
R114 0x72026F R113 0x710000 R112 0x700000 R111 0x6F0000 R110 0x6E0000 R109 0x6D0000 R108 0x6C00F1 R107 0x6B0000 R106 0x6A0007 R105 0x694440 R104 0x680000 R103 0x670000 R102 0x660000 R101 0x650000 R100 0x640000 R99 0x630000 R98 0x620000 R97 0x610000 R96 0x600000 R95 0x5F0000 R94 0x5E0000 R93 0x5D0000 R92 0x5C0000 R91 0x5B0000 R90 0x5A0000 R89 0x590000 R88 0x580000 R87 0x570000 R86 0x560000 R85 0x550000 R84 0x540000 R83 0x530000 R82 0x520000 R81 0x510000 R80 0x500000 R79 0x4F0000 R78 0x4E0064 R77 0x4D0000 R76 0x4C000C R75 0x4B0AC0 R74 0x4A0000 R73 0x49003F R72 0x480001 R71 0x470080 R70 0x46C350 R69 0x450000 R68 0x4403E8 R67 0x430000 R66 0x4201F4 R65 0x410000 R64 0x401388 R63 0x3F0000 R62 0x3E0322 R61 0x3D00A8 R60 0x3C09C4 R59 0x3B0001 R58 0x3A8001 R57 0x390020 R56 0x380000 R55 0x370000 R54 0x360000 R53 0x350000 R52 0x340420 R51 0x330080 R50 0x320000 R49 0x314180 R48 0x300300 R47 0x2F0300 R46 0x2E07FC R45 0x2DC0DF R44 0x2C1F23 R43 0x2B0000 R42 0x2A0000 R41 0x290000 R40 0x280000 R39 0x270001 R38 0x260000 R37 0x258404 R36 0x242800 R35 0x230004 R34 0x220000 R33 0x211E21 R32 0x200393 R31 0x1F43EC R30 0x1E318C R29 0x1D318C R28 0x1C0488 R27 0x1B0002 R26 0x1A0DB0 R25 0x190624 R24 0x18071A R23 0x17007C R22 0x160001 R21 0x150401 R20 0x14D848 R19 0x1327B7 R18 0x120064 R17 0x11012C R16 0x100080 R15 0x0F064F R14 0x0E1E70 R13 0x0D4000 R12 0x0C5001 R11 0x0B00A8 R10 0x0A10D8 R9 0x090604 R8 0x082000 R7 0x0700B2 R6 0x067802 R5 0x0503E8 R4 0x040E43 R3 0x030642 R2 0x020500 R1 0x010808 R0 0x002014
Hi Jaehueng,
I opened up your .tcs file and get the following: 
Your PFD frequency is extremely low at around 1MHz and your VCO_SEL is incorrect.
This does not seem to match your PLLatinumSim settings because in TICS you're using a 10.23MHz input where as in PLLatinumSim you have a 100MHz input clock.
Can the unoptimized loop filter coefficients cause the output to be muted?
Unoptimized loop filter design can can cause you to lose lock. Outputs being muted is not the same as having the device losing lock due to instability. Mute is simply a feature that "turns off" the RF output whenever a calibration is occurring.
What is your reference clock so I may provide an optimized loop filter configuration?
What is your application goal? Do you wish to have the widest loop bandwidth for faster lock times or do you wish to optimize for best jitter performance?
If I assume you wish to optimize jitter using a 100MHz reference clock you would use the following loop filter. 
Are you using the LMX2615-SP EVM?
If you are using the EVM - does loading the EVM default configuration with a 100MHz input allow you to lock the device?
Regards,
Vicente
Thanks for your response.
1) I sent the wrong files. So I resend the load files.
Reference input frequency: 10.23MHz
RFout frequency: 81.84MHz
VCO_SEL: VCO7
Could you review again using the corrected values?
2) Reset values
When the reference frequency enters the device, is the RFout generated with default values?
3)Fpd
You said that Fpd is extremely low. Can this value cause wrong functionality?
Hi Jaeheung,
I have attached a revised config.
Please let me know if this works and if you have achieved lock.
It is always preferable to use the largest PFD frequency possible which in effect allows you to use the lowest N divider value for best phase noise performance
If you PFD is too low - this can cause locking issues.
Toggle Fcal_EN after changing VCO frequency to trigger a calibration.
If possible can you use a 100MHz ref clk? You will achieve much better performance vs 10.23MHz input. 
Are you evaluating the LMX2615-SP EVM?
Regards,
Vicente
Hi Vicente
When I set 0x201C to the register R0, MUX OUT_LD_SEL=1, I can obtain lock state '1' from the pin MUXout.
When I set 0x2018 to register R0, MUX OUT_LD_SEL=0, I can obtain rb_LD_VTUNE 0x2 (Locked) from register R110.
However, there is no RFout or extraordinary noise output.
So, I cannot find any clue why the RFout is abnormal.
Could you present the way to have a normal output?
If you try loading the default config, can you achieve lock? 
Regards,
Vicente
Hi Vicente
We have an unlocked state from the pin MUXout.
We have a value of '11' Unlocked (Fvco High) from the register R110 rb_LD_VTUNE.
However, as I mentioned, your load file for the reference clock of 10.23MHz is locked.
Regardless of the lock status, the output is the same.
Moreover, even when setting a reset, making all register values '0', the same pattern is outputted.
Is there any way to create the normal RFout?
Can this be regarded as a broken chipset?
RFout A
RFout B
Hi Jaeheung,
As Noel mentioned we are not sure if you received feedback from local FAE.
I wanted to ask some questions after reviewing your schematic.
I see you have a differential 100Ohm resistor at OSCin pins but the text box says the input is single ended?
If operating single ended - I wouldn't expect the 100 differential resistor and the unused input should be AC shorted to GND or i.e. capacitor followed by series 50 Ohm resistor to GND. 
In the default mode, MUXOUT_LD_SEL is set to Lock Detect not readback. Was this register changed after loading the default configuration to enable readback? What you describe of all registers being '0' sounds like a readback was attempted while MUXOUT_LD_SEL was set to Lock detect not readback.
Can you please provide you start up sequence step by step including programming?
Regards,
Vicente
One more thing,
I see there is an email thread ongoing,
Noel commented on the output being incorrect.
You can use either a resistive pull up for good impedance matching or an inductive pull up for higher output power at the cost of matching. 
I will screenclip Noel's reply where he show's the resistors from the schematic that should not be placed & R188 should be swapped to 0Ohm.
Regards,
Vicente
