Other Parts Discussed in Thread: TLK2711-SP
Tool/software:
Hello,
Im using the CDCM7005-SP as a buffer to clock 4 TLK2711-SP devices. Here is the current setup:
1. VCC, AVCC, and VIN_CP = 3.3V
2. VCXO input is 125MHz also powered by 3.3V.
3. Output is LVCMOS
As can be seen in the scope capture below, the Purple (CH3) is the input reference Clock. The Green (CH4) is the output clock. As can be seen on CH4 is that the PK-PK voltage of the output clock is very large. With a Pk-Pk voltage upwards to 4.5V. But since CDCM7005-SP is powered by 3.3V, and according to the datasheet the output Pk-Pk should be VCC-0.1, or 3.2V.
My first thought is that the charge pump is not operating correctly? Looking at the functional block diagram it looks like the Charge pump is powering the output buffer. So if that we unstable/not regulating correctly would that explain the larger voltage swing of the output than the supply voltage? The CP_OUT pin is currently floating on the schematic so not sure if that would cause instability.
Thank you
Albert
