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Original question:

CDCE6214-Q1: cdce6214-q1

CDCE6214-Q1: NVMSCRC not computing

Alexandre L
Prodigy 10 points
Part Number: CDCE6214-Q1

Tool/software:

Hello,

I am currently trying to load a configuration into the EEPROM of a CDCE6214Q1 with direct access flow.

When rebooting, the CDCE loads the configuration we want from its EEPROM (correct outputs/frenquencies) and the NVMLCRC updates but not the NVMSCRC, which stays at 0x0000.

I have looked at a similar thread: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1282169/cdce6214-q1-cdce6214-q1

but the UPDATE_CRC R3[12] / power cycles don't change it, no matter how much times I do it.

I have this problem on 2 devices with different configurations.

Do you have any idea of what could be the reason here please?

Regards,

Alexandre

  • 0
    TI__Expert 3125 points

    Alexandre,

    Can you provide the EEPROM files that you are seeing these issues with?

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    Prodigy 10 points

    Hello Cris,

    Please find below every access I am doing. I am doing the register commit flow, and not direct access as previously stated.

    0055 ; 0000  
    0054 ; 0000  
    0053 ; 0000  
    0052 ; 0000  
    0051 ; 0004  
    0050 ; 0000  
    004F ; 0208  
    004E ; 1000  
    004D ; 0000  
    004C ; 0008  
    004B ; 0008  
    004A ; A181  
    0049 ; 2000  
    0048 ; 0004  
    0047 ; 0006  
    0046 ; 0008  
    0045 ; A181  
    0044 ; 3000  
    0043 ; 4005  
    0042 ; 0000  
    0041 ; 0008  
    0040 ; A181  
    003F ; 2000  
    003E ; 4005  
    003D ; 0000  
    003C ; 6008  
    003B ; 0008  
    003A ; 502C  
    0039 ; 4000  
    0038 ; 4005  
    0037 ; 001E  
    0036 ; 3400  
    0035 ; 0069  
    0034 ; 5000  
    0033 ; 40C0  
    0032 ; 07C0  
    0031 ; 0013  
    0030 ; 23C7  
    002F ; 03A0  
    002E ; 0000  
    002D ; 4F80  
    002C ; 0318  
    002B ; 0051  
    002A ; 0002  
    0029 ; 0000  
    0028 ; 0000  
    0027 ; 0000  
    0026 ; 0000  
    0025 ; 0000  
    0024 ; 0000  
    0023 ; 0000  
    0022 ; 0000  
    0021 ; 2710  
    0020 ; 0000  
    001F ; 0000  
    001E ; 0064  
    001D ; 0000  
    001C ; 0000  
    001B ; 0004  
    001A ; 0000  
    0019 ; 0401  
    0018 ; 0024  
    0017 ; 0000  
    0016 ; 0000  
    0015 ; 0000  
    0014 ; 0000  
    0013 ; 0000  
    0012 ; 0000  
    0011 ; 26C4  
    0010 ; 921F  
    000F ; A037  
    000E ; 0000  
    000D ; 0000  
    000C ; 0000  
    000B ; 0000  
    000A ; 0000  
    0009 ; 0000  
    0008 ; 0000  
    0007 ; 0C0D  
    0006 ; 0000  
    0005 ; 0000  
    0004 ; 0000  
    0003 ; 0000  
    0002 ; 0000 ;
    0001 ; 2310
    0000 ; 3010 ; "RECAL: Add x0010 to force PLL recalibration"
    0003 ; 0200 ; "Select the EEPROM page, to copy the register settings into, using REGCOMMIT_PAGE (page 1, HW_SW_CTRL being pull-up)"
    000F ; 5037 ; "Unlock the EEPROM for write access with EE_LOCK = x5"
    0003 ; 0600 ; "Start the register commit operation by writing 1 to REGCOMMIT."
    000E ; 003F ; "ENVM WR access for CRC (addr)"
    000D ; 928E ; "ENVM WR access for CRC (data)"

    Regards,

    Alexandre

  • 0 in reply to Alexandre L
    TI__Expert 3125 points

    Alexandre,

    Thank you for the clarification. 

    I noticed in the steps you sent, the CRC update step [Step 6 in the datasheet] seems to be missing. 

    Is this a typo? If the step is included in the EEPROM programming process, does the issue still occur?

    Best,

    Cris