Original question:
Tool/software:
Hi,
I am using CDCE6214-Q1 for 16.667MHz clock generation.
For testing purposes I need to introduce some jitter to the clock. I have tried enabling spread spectrum but I donot see any difference in the output clock.
Can you guide me to the correct settings?
thanks,
Jawaid
Jawaid,
SSC is generated through the fractional-N PLL. So the PLL must be set to Fractional mode in order for SSC to be enabled. See this default config as an example:
The sequence should be: disable SSC -> adjust PLL and SSC settings as desired -> recalibrate PLL -> enable SSC
If toggling SSC, the PLL must be recalibrated each time.
Additionally, make sure the Spread type selected matches the PFD being used.
Best,
Cris
