LP-MSPM0G3507: Generate phase-shift PWMs

David Lima

Tool/software:

Hi all,

I'm trying to generate two PWMs with the same frequency but different duties, shifting 50% to avoid overlapping when duty < 50%.

To do that, I'm using TIMA0 and TIMA1 and their configurations just before starting the counters are:

TIMA0

TIMA1

Both timers have the same period, 655
TIMA1 CTR value is initialized to 327 (655/2), to start counting shifted 50%.
Both CTRCTL.CVAE values are 1h (Do not change CTR when EN is activated)

When I activate both counters, I do not see the effects of shifting the counter by software

The CVAE value has been ignored since when the CTRL.EN bit changes to 1, the CTR is reset.

Additional info:

Both TIMA0/TIMA1 have the same clock source.
Timers never started before this CVAE/CTR write operations.

What is missing here?

Is there any other way to generate shifted PWMs avoiding overlapping? The requirements are:

Up to 4 PWMs
Each PWM could have a different duty
They shall be synchronized

Many thanks!

Best regards,

David

over 1 year ago

0 Luke Ledbetter over 1 year ago

TI__Mastermind 26940 points

Hi David,

2 potential alternative solutions using a single Timer:

The advanced timer's (TimerA) have a complementary output with a dead-band, the complementary will invert the inputs and the dead-band adds delay so both sets are never high at the same time. The complementary will have a duty cycle slightly less than your original PWM as it is the same frequency but reduced high-time based on the dead-band settings.

Alternatively you can set 2 (or 4) PWM CC channels so they have the same frequency and change their CC value so they have a different duty cycle, you can then invert one channel so it starts high and the other starts low. If they both need to idle low, you can force the bits (forcing will cause the output to be the value you set).

---

For the configuration you have, there doesn't seem to be any inherent delay between the 2 timers so when you start them they are synchronized, but they both start low and have the same duty cycle. I suggest using the phase load option to have the timer counter load in the phase value to introduce the phase shift here. (You can set TimerA1's phase load to the 327 value). For the timer count, I would check the registers while they're running to see if your TimerA1 is actually adopting the 327 count (I'm suspecting it is getting zero'd)

Regards,
Luke

0 David Lima over 1 year ago in reply to Luke Ledbetter

Prodigy 10 points

Hi Luke!

Thanks for your fast response.

I'm not sure if your solutions will satisfy the requirements since each PWM has different duty cycles, so overlapping occurs if duty > 50%. I will check them anyway.

Regarding my configuration, you are right, it seems that the CTR is zeroed when the EN bit is set, but according to the technical reference the CTRL.CVAE is controlling the event when enabling the counter:

But my application is not working as expected. When I stop the execution just before activating the CTRCTL.EN, all the registers are correctly filled (check the screenshots in the ticket) but the CTR seems to be reset to zero anyway.

My reference is: ti.com/lit/ug/slau846a/slau846a.pdf?ts=1727983891955

Thanks,

David

+1 Luke Ledbetter over 1 year ago in reply to David Lima

TI__Mastermind 26940 points

Hi David,

I did a quick mock-up of your idea on my end, will need a little adjusting to get what you want but I'm able to have my TimerA0 and TimerA1 non-sync'd with each other. I'm using 2 different CC channels per device with the configurations from the timx_timer_mode_pwm_center_stop example. (If you use this example, make sure to change the low-power mode from STOP to SLEEP so the TimerAs are still on).