Tool/software:
Hi,
The input frequency to clock buffer is 1800MHz and we plan to connect CLKOUT pins to FPGA and set them at output frequency of 225MHz.
The CLKOUT pins seem to be similar to CML standard. FPGA can support LVDS as below:
It also supports below highlighted differential standards.
So, can you please share which standard to use at FPGA's input side to meet CLKOUT's output standard?
Also pls recommend what type of termination needs to be used between these two interface standards?
Thanks