Other Parts Discussed in Thread: CDCE6214
Tool/software:
When using REFP/N as the reference, I'm seeing that the phase between the output clocks and the input reference appears to depend on the reference frequency.
I think I've programmed the PLL correctly; I have ip_rdiv set to 1 ; I'm setting pll_ndiv and pll_psfb to get f_vco in the allowed range. My input frequency is between 1 and 100 MHz. I have the sync_en bits set.
When I change the input frequency, I apply new PLL parameters as required and do a re-sync. What I observe is that the relative phase between the reference and output clocks is highly dependent on the frequency.
To illustrate, when the input clock is 5 MHz I get this:
And when it's 30 MHz I get this:
Top (black) is the input reference, bottom (blue) is the PLL output clock. In this case, output frequency = input frequency but that's just to better illustrate the issue; in my application that's not always the case.
As I increase the reference frequency, the phase offset moves in a very regular, monotonic manner.
The PLL is locked (it claims to be, and it appears to be), and this is 100% reproducible (for a given frequency I always get the same phase).
Is this the intended behaviour? Is there anything I can do to get a fixed phase relationship?
I know I can use output sync_delay feature but I don't think that's a complete solution since the adjustment is rather coarse and limited in range.
